15.3.1.1 PHY Interface
The Ethernet Controller module and Integrated PHY receive two clock inputs, as follows:
- A gated system clock acts as the clock source to the Control and Status registers (CSR) of the Ethernet MAC. The SYSCLK frequency for run, sleep, and deep sleep modes is programmed into the System Control module. See Section 4 for more information on programming SYSCLK and enabling the Ethernet MAC.
- The PHY receives the main oscillator (MOSC) which must be 25 MHz ±50 ppm for proper operation. The MOSC source can be a single-ended source or a crystal. Figure 15-2 shows the clock inputs to the Ethernet Controller module.