4.2.17 PIOSCCAL Register (Offset = 0x150) [reset = 0x0]
Precision Internal Oscillator Calibration (PIOSCCAL)
This register provides the ability to update or recalibrate the precision internal oscillator. A 32.768-kHz oscillator must be used as the clock source of the Hibernation module for the user to calibrate the PIOSC.
PIOSCCAL is shown in Figure 4-23 and described in Table 4-29.
Return to Summary Table.
Figure 4-23 PIOSCCAL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| UTEN |
RESERVED |
| R/W-0x0 |
R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
CAL |
UPDATE |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
UT |
| R-0x0 |
R/W-0x0 |
|
Table 4-29 PIOSCCAL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31 |
UTEN |
R/W |
0x0 |
Use User Trim Value
0x0 = The factory calibration value is used for an update trim operation.
0x1 = The trim value in bits [6:0] of this register are used for any update trim operation.
|
| 30-10 |
RESERVED |
R |
0x0 |
|
| 9 |
CAL |
R/W |
0x0 |
Start Calibration.
This bit is auto-cleared after it is set.
0x0 = No action
0x1 = Starts a new calibration of the PIOSC. Results are in the PIOSCSTAT register. The resulting trim value from the operation is active in the PIOSC after the calibration completes. The result overrides any previous update trim operation whether the calibration passes or fails.
|
| 8 |
UPDATE |
R/W |
0x0 |
Update Trim.
This bit is automatically cleared after the update.
0x0 = No action
0x1 = Updates the PIOSC trim value with the UT bit or the DT bit in the PIOSCSTAT register. Used with UTEN.
|
| 7 |
RESERVED |
R |
0x0 |
|
| 6-0 |
UT |
R/W |
0x0 |
User Trim Value.
User trim value that can be loaded into the PIOSC.
|