SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
PLL Frequency 0 (PLLFREQ0)
This register always contains the variables used to configure the PLL. If the PLL is reprogrammed, it must go through a relock sequence which is defined by the parameter tREADY in the device-specific data sheet. When controlling this register directly, software must change this value while the PLL is powered down. Writes to PLLFREQ0 are delayed from affecting the PLL until the RSCLKCFG register NEWFREQ bit is written with a 1.
The PLL frequency can be calculated using Equation 3.
where
The Q and N values are programmed in the PLLFREQ1 register. To reduce jitter, program MFRAC to 0x0.
PLLFREQ0 is shown in Figure 4-25 and described in Table 4-31.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PLLPWR | RESERVED | MFRAC | |||||
| R/W-0x0 | R-0x0 | R/W-0x0 | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| MFRAC | MINT | ||||||
| R/W-0x0 | R/W-0x0 | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MINT | |||||||
| R/W-0x0 | |||||||