6.3.9 Power Control Using VDD3ON Mode
The Hibernation module may also be configured to cut power to all internal modules during Hibernate mode. While in this state, if VDD3ON is set in the HIBCTL register, all pins are held in the state they were in prior to entering hibernation. For example, inputs remain inputs; outputs driven high remain driven high, and so on. There are important procedural and functional items to note when in VDD3ON mode:
- JTAG Ports C[0] - C[3] do not retain their state in Hibernate VDD3ON mode.
- If GPIO pins K[7:4] are not used as a wake source, they should not be left floating. An internal pullup resistor may be configured by the application before entering Hibernate mode by programming the GPIO Pull-Up Select (GPIOPUR) register in the GPIO module.
- In the VDD3ON mode, the regulator should maintain 3.3 V power to the microcontroller during Hibernate. GPIO retention is disabled when the RETCLR bit is cleared in the HIBCTL register.
- When entering hibernation in VDD3ON mode, the supply rails to the Ethernet resistors R1, R2, R3, R4 found in Figure 15-15 must be switched off.