SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
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7.2.3.2 Prefetch Buffers
The prefetch buffers can exist as a single set of 2 × 256-bit buffers or 4 × 256-bit buffers, depending on the SPFE bit programmed in the Flash Configuration (FLASHCONF) register at offset 0xFC8. At reset, all four buffers are enabled. The buffers are filled using a least-recently-used (LRU) method. When operating in a single set buffer configuration, the two, 256-bit buffers create a deterministic configuration as each next write is sent to the previous buffer that was written. Figure 7-4 depicts the single 256-bit buffer set. The single prefetch buffer set should only be used when the code execution must be purely deterministic for the number of clock cycles it takes to execute. Using the four prefetch buffer configuration is the preferred method of configuration.
Figure 7-4 Single 256-Bit Prefetch Buffer Set When the buffers are configured as four, 256-bit buffers, they function as one set with one of the four buffers tagged as the LRU and the next to be used when an autofill or miss occurs.
Figure 7-5 Four 256-Bit Prefetch Buffer Configuration The address of the autofill is stored in this tag register so that address violations can be identified immediately and miss processing can begin directly. Every ICODE access is checked against valid tags to see if the target word is already in the buffers.
If there is a hit, the target word is immediately sent to the CPU with no wait states. If there is a miss, the prefetch buffer is invalidated and the miss is processed as a 256-bit read from the flash subsystem to fill the next, least-recently used prefetch buffer. Two memory banks are read in parallel to retrieve 256-bits worth of data.
If an autofill has been started and a miss occurs, the autofill completes before the miss is processed. If an autofill occurs that hits the prefetch buffer being processed for the autofill, then the ICODE bus is stalled until the autofill is complete and new entry can be accessed. For an instruction miss, access to the flash bank starts immediately after the address is available, provided the flash subsystem is not already processing a DCODE bus access or a program or erase operation in the same banks. The target word is passed to the CPU one cycle after it is written to the prefetch buffer.
Figure 7-6 shows the timing diagram for a hit in the prefetch buffer.
Figure 7-6 Single Cycle Access, 0 Wait States The flash memory can operate at the CPU clock speed with zero-wait-state accesses when data is resident in the prefetch buffers. When an access does not hit in the prefetch buffer, there is a delay that is incurred while the data is transferred from the flash. This delay is dependent on the programmed CPU frequency. See Table 7-1 for required CPU frequency versus programmed wait-state delay information. Figure 7-7 shows the events that occur as the CPU steps through the words in the prefetch buffer that has just been loaded until it reaches the end of the current prefetch line. The notable events follow (see Figure 7-7):
- EVENT A: When the CPU has a miss in the prefetch buffer, a line is fetched from flash. The target word is written to the prefetch buffer and sent to the CPU one cycle after.
- EVENT B: When the CPU reaches Word 3, the next 256-bit buffer line is fetched, resulting in a zero-wait-state access of word 0 of the next line.
- EVENT C: After this word, if the CPU is still executing sequentially, word 0 of the next buffer line that was fetched is sent to the CPU with zero-wait-state delay.
- EVENT D: Word 0 from the second fetch that occurred is sent to the CPU.
Figure 7-7 Prefetch Fills From Flash If the CPU target word is beyond word 2 (word 3 through word 7) then the next prefetch fill begins immediately, and, depending on the CPU frequency, a delay is incurred between CPU access of word 7 and word 0 of the next line.
NOTE
For optimal prefetch buffer performance, align application code and branches on 8-word boundaries.
NOTE
Because the prefetch buffers and flash memory can effectively be used at 20 MHz and higher, an application can have an improvement in current consumption from 16 MHz to 20 MHz.
The prefetch buffers can be forced ON and OFF by setting the FPFON and FPFOFF bits in the Flash Configuration (FLASHCONF) register at 0xFC8. If the application sets the FPFON or FPFOFF bit while the CPU is currently reading or writing to flash, the prefetch buffer action of turning on or off happens only after the flash operation has completed. This feature can be used in test modes when determining optimum memory configuration for code.
Prefetch buffer valid tags can be cleared in the following ways:
- Any Flash Configuration (FLASHCONF) register changes, such as:
- Disabling the prefetch buffer by setting the FPFOFF bit
- Setting the CLRTV bit to clear the prefetch buffer tags
- A system reset
- ROM accesses
- Error during ICODE accesses
- System aborts
- Mirror mode changes
NOTE
If the prefetch buffers are enabled and application code branches to a location other than flash memory which then modifies the flash memory, the prefetch tags must be cleared before returning to flash code execution. Prefetch buffer valid tags can be cleared by setting the CLRTV bit in the FLASHCONF register.