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16.4.3.2 PSRAM Support
The EPI host bus supports both a synchronous and asynchronous interface to PSRAM memory when configured in 16-bit bus multiplexed mode. The EPIHBPSRAM register holds the values for the PSRAM bus configuration (CR) registers. The contents of the EPIHBPSRAM register can be sent to different memories depending on which WRCRE or RDCRE bit is set in the various EPIHB16CFGn registers. For example, if the WRCRE bit is enabled in EPIHB16CFG, then the CRE signal asserts and the contents are sent to the memory enabled by CS0. Enabling the WRCRE or RDCRE bit in EPIHB16CFG2 register activates CS1n during a PSRAM configuration register write or read. The WRCRE and RDCRE bit in EBIHB16CFG3 corresponds to CS2n and EPIHB16CFG4, to CS3n. The WRCRE bit clears when the transfer is done. There must not be any system access or nonblocking read activity during the CRE read or write-enable transfer. During a write to the PSRAM's CR, the configuration data is written out on data pins [20:0] of the EPI bus. For a PSRAM configuration read access, the RDCRE bit in the EPIHB16CFG register is set to signal that the next access is a read of the PSRAM configuration register (CR). The address for the CR is written to bits CR[19:18] of the EPIHBPSRAM register. The read data is returned at CR bits [15:0] of the EPIHBPSRAM register.
NOTE
- CRE read and write operations may only occur in asynchronous mode. During synchronous mode the CRE bit should be disabled. Setting the CRE bit during synchronous PSRAM accesses can lead to unpredictable behavior.
- When the chip select is programmed to access the PSRAM, the MODE bit of the EPIHBnCFGn register must be programmed to enable address and data muxed (ADMUX). Page mode accesses are not supported by the EPI.
- BURST is optimized for word-length bursting for SDRAM and PSRAM accesses.
These steps initialize the PSRAM interface:
- Perform the EPI initialization steps in Section 16.4.
- Enable host bus 16 mode by setting the MODE bits in the EPICFG register to 0x13. Choose between an integer or formula clock divide for the baud rate by configuring the INTDIV bit in the EPICFG register.
- Configure the EPIBAUD register to the desired baud rate.
- Because the EPI module supports only asynchronous programming of the configuration registers, clock gate the EPI clock by programming both the CLKGATE and CLKGATEI bits in the EPIHB16CFG register to 0.
- Prepare for writing the PSRAM Bus Configuration register by setting the ALEHIGH = 1 and MODE = 0x0 in the EPIHB16CFG register.
- Program the EPIHBPSRAM register to be loaded into the CR register of the PSRAM by configuring bits [21:0].
- CR[20:19] = 0x0, reserved
- CR[19:18] = 0x2 to enable configuring of the CR register
- CR[15]= 0x1 to enable asynchronous access
- CR [14] = 0 if the iRDY signal is used for memory transfers; if the design will not use the iRDY signal CR[14] should be cleared.
- CR[13:11] must be programmed to have a matching read and write wait state configuration as is programmed in the EPIHB16CFG and EPIHB16TIME register.
- CR[10] configures the polarity of the WAIT signal and should match the configuration of the IRDYINV bit in the EPIHB16CFG register.
- CR[8]= 0x1 to configure the appropriate wait configuration of the data
- CR[2:0]= 0x7 since the EPI interface in PSRAM mode is a continuous burst access.
- Set the WRCRE bit in the EPIHB16CFGn register to initiate a write from the EPIHBPSRAM register to the PSRAM CR register.
NOTE
If the PSRAM CR register must be reprogrammed after initialization, the application should allow the previous transfer to complete before beginning configuration to ensure proper PSRAM functionality.
Table 16-9 PSRAM Fixed Latency Wait State Configuration
| Latency Counter | Latency in Clocks | RDWS[1:0]/WRWS[1:0] | RWSM/WRWSM |
|---|---|---|---|
| BCR Code 2 | 3 | 0x0 | 0 |
| BCR Code 3 | 4 | 0x1 | 1 |
| BCR Code 4 | 5 | 0x1 | 0 |
| BCR Code 5 | 6 | 0x2 | 1 |
| BCR Code 6 | 7 | 0x2 | 0 |
| BCR Code 8 | 9 | 0x3 | 0 |
In variable initial latency mode, the memory's WAIT (iRDY) pin guides the EPI module when to read and write. The WAIT (iRDY) pin stalls the access for the duration of the latency and adds cycles if there is a refresh collision. To get the best performance, set CR[13:11] = 0x2, the WRWS field of the EPIHB16CFG register to 0x0, and the WRWSM and RDWSM bit of the EPI16TIMEn register to 0. For the WAIT pin to be recognized correctly, set the IRDYDLY bit in the EPI16TIMEn register to 1 and the CR[8] = 1 in the EPIHBPSRAM register.
NOTE
Wait state latency works differently in PSRAM Burst mode than in other modes. In PSRAM Burst mode, the RDWS and WRWS bit fields define the latency for only the first access of the write or read cycle. Every access after that is a single access.
Figure 16-7 and Figure 16-8 depict a PSRAM burst read and write.
Figure 16-7 PSRAM Burst Read 
Figure 16-8 PSRAM Burst Write If a read or write transfer attempts to begin during a refresh event, the transfer is held off by the assertion of the iRDY pin by the memory to the EPI module. Figure 16-9 and Figure 16-10 depict the delay in data transfer during a refresh collision.
Figure 16-9 Read Delay During Refresh Event 
Figure 16-10 Write Delay During Refresh Event