SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a 24-bit down counter with a start value (and thus period) defined by the GPTMTnILR and GPTMTnPR registers. In this mode, the PWM frequency and period are synchronous events and therefore guaranteed to be glitch-free. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. Table 18-8 lists the values that are loaded into the timer registers when the timer is enabled.
Register | Count Down Mode | Count Up Mode |
---|---|---|
GPTMTnR | GPTMTnILR | Not available |
GPTMTnV | GPTMTnILR | Not available |
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0 state. Alternatively, if the TnWOT bit is set in the GPTMTnMR register, once the TnEN bit is set, the timer waits for a trigger to begin counting (see Section 18.3.4). On the next counter cycle in periodic mode, the counter reloads its start value from the GPTMTnILR and GPTMTnPR register s and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. The timer is capable of generating interrupts based on three types of events: rising edge, falling edge, or both. The event is configured by the TnEVENT field of the GPTMCTL register, and the interrupt is enabled by setting the TnPWMIE bit in the GPTMTnMR register. When the event occurs, the CnERIS bit is set in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode event interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the CnEMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register. The interrupt status bits are not updated unless the TnPWMIE bit is set.
In addition, when the TnPWMIE bit is set and a capture event occurs, the Timer automatically generates triggers to the ADC and DMA if the trigger capability is enabled by setting the TnOTE bit in the GPTMCTL register and the CnEDMAEN bit in the GPTMDMAEV register, respectively.
In this mode, the GPTMTnR and GPTMTnV registers always have the same value.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR and GPTMTnPR registers (its start state), and is deasserted when the counter value equals the value in the GPTMTnMATCHR and GPTMTnPMR registers. Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register.
NOTE
If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a positive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal.
Figure 18-4 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML = 0 (duty cycle would be 33% for the TnPWML = 1 configuration). For this example, the start value is GPTMTnILR = 0xC350 and the match value is GPTMTnMATCHR = 0x411A.
When synchronizing the timers using the GPTMSYNC register, the timer must be properly configured to avoid glitches on the CCP outputs. Both the TnPLO and the TnMRSU bits must be set in the GPTMTnMR register. Figure 18-5 shows how the CCP output operates when the TnPLO and TnMRSU bits are set and the GPTMTnMATCHR value is greater than the GPTMTnILR value.
Figure 18-6 shows how the CCP output operates when the PLO and MRSU bits are set and the GPTMTnMATCHR value is the same as the GPTMTnILR value. In this situation, if the PLO bit is 0, the CCP signal goes high when the GPTMTnILR value is loaded and the match would be essentially ignored.
Figure 18-7 shows how the CCP output operates when the PLO and MRSU bits are set and the GPTMTnILR is greater than the GPTMTnMATCHR value.