SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070
PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0
PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0
PWM3 Dead-Band Falling-Edge-Delay (PWM3DBFALL), offset 0x130
The PWMnDBFALL register contains the number of clock cycles to delay the rising edge of the pwmB' signal from the falling edge of the pwmA signal. If the dead-band generator is disabled through the PWMnDBCTL register, this register is ignored. If the value of this register is larger than the width of a Low pulse on the pwmA signal, the falling-edge delay consumes the entire Low time of the signal, resulting in no Low time on the output. Care must be taken to ensure that the pwmA Low time always exceeds the falling-edge delay.
If the Dead-Band Falling-Edge-Delay mode is immediate (based on the DBFALLUP field encoding in the PWMnCTL register), the 12-bit FALLDELAY value is used immediately. If the update mode is locally synchronized, this value is used the next time the counter reaches zero. If the update mode is globally synchronized, this value is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see Section 21.5.1). If this register is rewritten before the actual update occurs, the previous value is never used and is lost.
PWMnDBFALL is shown in Figure 21-30 and described in Table 21-26.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | FALLDELAY | ||||||||||||||||||||||||||||||
| R-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||