SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C
PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC
PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC
PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset 0x12C
The PWMnDBRISE register contains the number of clock cycles to delay the rising edge of the pwmA signal when generating the pwmA' signal. If the dead-band generator is disabled through the PWMnDBCTL register, this register is ignored. If the value of this register is larger than the width of a High pulse on the pwmA signal, the rising-edge delay consumes the entire High time of the signal, resulting in no High time on the output. Care must be taken to ensure that the pwmA High time always exceeds the rising-edge delay.
If the Dead-Band Rising-Edge Delay mode is immediate (based on the DBRISEUPD field encoding in the PWMnCTL register), the 12-bit RISEDELAY value is used immediately. If the update mode is locally synchronized, this value is used the next time the counter reaches zero. If the update mode is globally synchronized, this value is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see Section 21.5.1). If this register is rewritten before the actual update occurs, the previous value is never used and is lost.
PWMnDBRISE is shown in Figure 21-29 and described in Table 21-25.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RISEDELAY | ||||||||||||||||||||||||||||||
| R-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||