SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
PWM0 Generator A Control (PWM0GENA), offset 0x060
PWM1 Generator A Control (PWM1GENA), offset 0x0A0
PWM2 Generator A Control (PWM2GENA), offset 0x0E0
PWM3 Generator A Control (PWM3GENA), offset 0x120
These registers control the generation of the pwmA signal based on the load and zero output pulses from the counter, as well as the compare A and compare B pulses from the comparators (PWM0GENA controls the PWM generator 0 block, and so on). When the counter is running in Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six occur. These events provide great flexibility in the positioning and duty cycle of the resulting PWM signal.
The PWM0GENA register controls generation of the pwm0A signal; PWM1GENA, the pwm1A signal; PWM2GENA, the pwm2A signal; and PWM3GENA, the pwm3A signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is taken and the compare A or compare B action is ignored. If a compare A event coincides with a compare B event, the compare A action is taken and the compare B action is ignored.
If the Generator A update mode is immediate (based on the GENAUPD field encoding in the PWMnCTL register), the ACTCMPBD, ACTCMPBU, ACTCMPAD, ACTCMPAU, ACTLOAD, and ACTZERO values are used immediately. If the update mode is locally synchronized, these values are used the next time the counter reaches zero. If the update mode is globally synchronized, these values are used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (seeSection 21.5.1). If this register is rewritten before the actual update occurs, the previous value is never used and is lost.
PWMnGENA is shown in Figure 21-26 and described in Table 21-22.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | ACTCMPBD | ACTCMPBU | |||||
| R-0x0 | R/W-0x0 | R/W-0x0 | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACTCMPAD | ACTCMPAU | ACTLOAD | ACTZERO | ||||
| R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | ||||