21.5.14 PWMnRIS Register [reset = 0x0]
PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048
PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088
PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8
PWM3 Raw Interrupt Status (PWM3RIS), offset 0x108
These registers provide the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0 block, and so on). If a bit is set, the event has occurred; if a bit is clear, the event has not occurred. Bits in this register are cleared by writing a 1 to the corresponding bit in the PWMnISC register.
PWMnRIS is shown in Figure 21-20 and described in Table 21-16.
Return to Summary Table.
Figure 21-20 PWMnRIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
INTCMPBD |
INTCMPBU |
INTCMPAD |
INTCMPAU |
INTCNTLOAD |
INTCNTZERO |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 21-16 PWMnRIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-6 |
RESERVED |
R |
0x0 |
|
| 5 |
INTCMPBD |
R |
0x0 |
Comparator B down interrupt status. This bit is cleared by writing a 1 to the INTCMPBD bit in the PWMnISC register.
0x0 = An interrupt has not occurred.
0x1 = The counter has matched the value in the PWMnCMPB register while counting down.
|
| 4 |
INTCMPBU |
R |
0x0 |
Comparator B up interrupt status. This bit is cleared by writing a 1 to the INTCMPBU bit in the PWMnISC register.
0x0 = An interrupt has not occurred.
0x1 = The counter has matched the value in the PWMnCMPB register while counting up.
|
| 3 |
INTCMPAD |
R |
0x0 |
Comparator A down interrupt status. This bit is cleared by writing a 1 to the INTCMPAD bit in the PWMnISC register.
0x0 = An interrupt has not occurred.
0x1 = The counter has matched the value in the PWMnCMPA register while counting down.
|
| 2 |
INTCMPAU |
R |
0x0 |
Comparator A up interrupt status. This bit is cleared by writing a 1 to the INTCMPAU bit in the PWMnISC register.
0x0 = An interrupt has not occurred.
0x1 = The counter has matched the value in the PWMnCMPA register while counting up.
|
| 1 |
INTCNTLOAD |
R |
0x0 |
Counter=Load interrupt status. This bit is cleared by writing a 1 to the INTCNTLOAD bit in the PWMnISC register.
0x0 = An interrupt has not occurred.
0x1 = The counter has matched the value in the PWMnLOAD register.
|
| 0 |
INTCNTZERO |
R |
0x0 |
Counter=0 interrupt status. This bit is cleared by writing a 1 to the INTCNTZERO bit in the PWMnISC register.
0x0 = An interrupt has not occurred.
0x1 = The counter has matched zero.
|