SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
PWM Time Base Sync (PWMSYNC)
This register provides a method to perform synchronization of the counters in the PWM generation blocks. Setting a bit in this register causes the specified counter to reset back to 0; setting multiple bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred; reading them back as zero indicates that the synchronization has completed.
PWMSYNC is shown in Figure 21-8 and described in Table 21-4.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SYNC3 | SYNC2 | SYNC1 | SYNC0 | |||
R-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | |||