| 31-20 |
RESERVED |
R |
0x0 |
|
| 19-16 |
FILTCNT |
R/W |
0x0 |
Input Filter Prescale Count. This field controls the frequency of the input update. When this field is clear, the input is sampled after 2 system clocks. When this field ix 0x1, the input is sampled after 3 system clocks. Similarly, when this field is 0xF, the input is sampled after 17 clocks.
|
| 15-14 |
RESERVED |
R |
0x0 |
|
| 13 |
FILTEN |
R/W |
0x0 |
Enable Input Filter.
0x0 = The QEI inputs are not filtered.
0x1 = Enables the digital noise filter on the QEI input signals. Inputs must be stable for 3 consecutive clock edges before the edge detector is updated.
|
| 12 |
STALLEN |
R/W |
0x0 |
Stall QEI.
0x0 = The QEI module does not stall when the microcontroller is stopped by a debugger.
0x1 = The QEI module stalls when the microcontroller is stopped by a debugger.
|
| 11 |
INVI |
R/W |
0x0 |
Invert Index Pulse.
0x0 = No effect.
0x1 = Inverts the IDX input.
|
| 10 |
INVB |
R/W |
0x0 |
Invert PhB.
0x0 = No effect.
0x1 = Inverts the PhBn input.
|
| 9 |
INVA |
R/W |
0x0 |
Invert PhA.
0x0 = No effect.
0x1 = Inverts the PhAn input.
|
| 8-6 |
VELDIV |
R/W |
0x0 |
Predivide Velocity. This field defines the predivider of the input quadrature pulses before being applied to the QEICOUNT accumulator.
0x0 = /1
0x1 = /2
0x2 = /4
0x3 = /8
0x4 = /16
0x5 = /32
0x6 = /64
0x7 = /128
|
| 5 |
VELEN |
R/W |
0x0 |
Capture Velocity.
0x0 = No effect.
0x1 = Enables capture of the velocity of the quadrature encoder.
|
| 4 |
RESMODE |
R/W |
0x0 |
Reset Mode.
0x0 = The position counter is reset when it reaches the maximum as defined by the MAXPOS field in the QEIMAXPOS register.
0x1 = The position counter is reset when the index pulse is captured.
|
| 3 |
CAPMODE |
R/W |
0x0 |
Capture Mode. When SIGMODE = 1, the CAPMODE setting is not applicable and is reserved.
0x0 = Only the PhA edges are counted.
0x1 = The PhA and PhB edges are counted, providing twice the positional resolution but half the range.
|
| 2 |
SIGMODE |
R/W |
0x0 |
Signal Mode.
0x0 = The internal PhA and PhB signals operate as quadrature phase signals.
0x1 = The internal PhA input operates as the clock (CLK) signal and the internal PhB input operates as the direction (DIR) signal.
|
| 1 |
SWAP |
R/W |
0x0 |
Swap Signals. Note if the INVA or INVB bit are set, the inversion of the signals occur prior to the swap.
0x0 = No effect.
0x1 = Swaps the PhAn and PhBn signals.
|
| 0 |
ENABLE |
R/W |
0x0 |
Enable QEI. After the QEI module has been enabled by setting the ENABLE bit, it cannot be disabled. The only way to clear the ENABLE bit is to reset the module using the Quadrature Encoder Interface Software Reset (SRQEI) register.
0x0 = No effect.
0x1 = Enables the quadrature encoder module.
|