20.3.2.1.2 Raster Mode
When operating in Raster mode, the DMA engine generates the interrupts in the following scenarios:
- Output FIFO under-run: This interrupt occurs when the DMA engine cannot keep up with the data rate consumed by the LCD (which is determined by the LCDCP.) This is likely due to a system memory throughput issue or an incorrect LCDCP setting. The FIFOU bit in LCD Interrupt Raw Status and Set Register (LCDRISSET) register is set when this error occurs. This bit is cleared by disabling the Raster Controller, that is clearing the LCDEN bit in LCD Raster Control (LCDRASTRCTL) register.
- Frame synchronization lost: This error happens when the DMA engine attempts to read what it believes to be the first word of the video buffer but the data cannot be recognized as such. This situation can be caused by an invalid frame buffer address or an invalid BPP value. The SYNC bit in the IRQSTATUS_RAW register is set when such an error is detected. This field is cleared by disabling the Raster Controller (clearing the LCDEN bit in LCD Raster Control (LCDRASTRCTL) register).
- Palette loaded: This interrupt can be generated when the palette is loaded into the memory by the DMA engine. At the same time, the PALLOAD bit in the LCD Interrupt Raw Status and Set Register (LCDRISSET) register is set. In data-only (PALMODE = 0x2) and palette-plus-data (PALMODE = 0x0) modes, writing 0 to this bit clears the interrupt. In the palette-only (PALMODE = 0x1) mode, this bit is cleared by disabling the Raster Controller (clearing the LCDEN bit in the LCD Raster Control (LCDRASTRCTL) register).
- AC bias transition: If the ACBI field in the LCD Raster Timing 2 (LCDRASTRTIM2) register is programmed with a nonzero value, an internal counter is loaded with this value and starts to decrement each time LCDAC (AC-bias signal) switches its state. When the counter reaches zero, the ACBS bit in the LCD Interrupt Raw Status and Set Register (LCDRISSET) register is set, which delivers an interrupt signal to the system interrupt controller (if the interrupt is enabled.) The counter reloads the value in ACBI field, but does not start to decrement until the ABC bit is cleared by writing 0 to this bit.
- Frame transfer completed: When one frame of data is transferred completely, the DONE bit in the LCD Interrupt Raw Status and Set Register (LCDRISSET) register is set. This bit is cleared by disabling the Raster Controller (clearing the LCDEN bit in LCD Raster Control (LCDRASTRCTL) register). The EOF0 and EOF1 bits in LCD Interrupt Raw Status and Set Register (LCDRISSET) register are set accordingly.
The function enable bits are in the in LCD Raster Control (LCDRASTRCTL) register and must be set to generate an interrupt to the CPU.