SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data using the legacy serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. If the receive FIFO is full when the master or slave receives new data, the data is held off until the receive FIFO has space.
The SSI only provides an SSIClk while transmitting data. When receiving data in master mode, a dummy write to the SSIDR register must be performed before any read so that the SSIClk can be properly received by the slave and allow data to be sent to the receive FIFO of the master.
When configured as a master or slave, serial data received through the SSInDAT1/SSInRX pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively.
NOTE
When operating in Legacy Mode, the SSInXDAT1 signal of QSSI functions as SSInRX.