15.3.1.3 Reduced Media-Independent Interface (RMII)
Three clock sources interface to the Ethernet MAC in an RMII configuration, as follows:
- Gated system clock (SYSCLK): The SYSCLK signal acts as the clock source to the Control and Status registers (CSR) of the Ethernet MAC. The SYSCLK frequency for Run, Sleep, and Deep Sleep mode is programmed in the System Control module. See Section 4 for more information on programming SYSCLK and enabling the Ethernet MAC.
- MOSC: A gated version of the MOSC clock is provided as the Precision Time Protocol (PTP) reference clock (PTPREF_CLK). The MOSC clock source can be a single-ended source on the OSC0 pin or a crystal on the OSC0 and OSC1 pins. When advanced timestamping is used and the PTP module has been enabled by setting the PTPCEN bit in the EMACCC register, the MOSC drives PTPREF_CLK. PTPREF_CLK has a minimum frequency requirement of 5 MHz and a maximum frequency of 25 MHz. See Section 15.3.6 for more information.
- EN0RREF_CLK: When using RMII, a 50-MHz external reference clock must drive the EN0RREF_CLK input signal and the external PHY. Depending on the configuration of the FES bit in the Ethernet MAC Configuration (EMACCFG) register, the reference clock input (EN0RREF_CLK) is divided by 20 for 10 Mbps, or 2 for 100 Mbps operation, and used as the clock for receive and transmit data.
Figure 15-4 shows the clock inputs to the RMII clock.