19.3.1.5.1 Repeated Start For Master Transmit
A repeated start sequence for a master transmit is as follows:
- When the device is in the idle state, the master writes the slave address to the I2CMSA register and configures the R/S bit for the desired transfer type.
- Data is written to the I2CMDR register.
- When the BUSY bit in the I2CMCS register is 0, the master writes 0x3 to the I2CMCS register to initiate a transfer.
- The master does not generate a STOP condition but instead writes another slave address to the I2CMSA register and then writes 0x3 to initiate the repeated START.