SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
SHA Data 0 Input (SHA_DATA_0_IN), offset 0x080
SHA Data 1 Input (SHA_DATA_1_IN), offset 0x084
SHA Data 2 Input (SHA_DATA_2_IN), offset 0x088
SHA Data 3 Input (SHA_DATA_3_IN), offset 0x08C
SHA Data 4 Input (SHA_DATA_4_IN), offset 0x090
SHA Data 5 Input (SHA_DATA_5_IN), offset 0x094
SHA Data 6 Input (SHA_DATA_6_IN), offset 0x098
SHA Data 7 Input (SHA_DATA_7_IN), offset 0x09C
SHA Data 8 Input (SHA_DATA_8_IN), offset 0x0A0
SHA Data 9 Input (SHA_DATA_9_IN), offset 0x0A4
SHA Data 10 Input (SHA_DATA_10_IN), offset 0x0A8
SHA Data 11 Input (SHA_DATA_11_IN), offset 0x0AC
SHA Data 12 Input (SHA_DATA_12_IN), offset 0x0B0
SHA Data 13 Input (SHA_DATA_13_IN), offset 0x0B4
SHA Data 14 Input (SHA_DATA_14_IN), offset 0x0B8
SHA Data 15 Input (SHA_DATA_15_IN), offset 0x0BC
Data input message
NOTE
The SHA_DATA_n_IN_0 register acts as a FIFO and shifts data into the other SHA_DATA_n_IN registers.
SHA_DATA_n_IN is shown in Figure 25-8 and described in Table 25-19.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA_IN | |||||||||||||||||||||||||||||||
| R/W-0x0 | |||||||||||||||||||||||||||||||