SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
SHA Interrupt Enable (SHA_IRQENABLE)
The SHA_IRQENABLE register contains an enable bit for each unique interrupt. An interrupt is enabled when both the global enable, the IT_EN bit, in the SHA_SYSCONFIG register and the bit in this register are both set to 1.
SHA_IRQENABLE is shown in Figure 25-13 and described in Table 25-24.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | M_CONTEXT_READY | RESERVED | M_INPUT_READY | M_OUTPUT_READY | |||
R-0x0 | R/W-0x0 | R-0x0 | R/W-0x1 | R/W-0x1 | |||