SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The slave module also has the capability to use the µDMA in Rx and Tx FIFO data transfers. If the Tx FIFO is assigned to the slave module and the TXFIFO bit is set in the I2CSCSR register, the slave module will generate a single µDMA request, dma_sreq, if the master module requests the next byte transfer. If the FIFO fill level is less than the trigger level, a µDMA multiple transfer request, dma_req, will be asserted to continue data transfers from the µDMA.
If the Rx FIFO is assigned to the slave module and the RXFIFO bit is set in the I2CSCSR register, then the slave module will generate a signal µDMA request, dma_sreq, if there is any data to be transferred. The dma_req signal will be asserted when the Rx FIFO has more data than the trigger level programmed by the RXTRIG bit in the I2CFIFOCTL register.
NOTE
Best practice recommends that an application should not switch between the I2CSDR register and TX FIFO or vice versa for successive transactions.