SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The order of instructions in the program flow does not always ensure the order of the corresponding memory transactions for the following reasons:
Section 1.5.2 describes the cases where the memory system ensures the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. The Cortex-M4F has the following memory barrier instructions:
Memory barrier instructions can be used in the following situations:
If the program changes an entry in the vector table and then enables the corresponding exception, use a DMB instruction between the operations. The DMB instruction ensures that if the exception is taken immediately after being enabled, the processor uses the new exception vector.
If a program contains self-modifying code, use an ISB instruction immediately after the code modification in the program. The ISB instruction ensures subsequent instruction execution uses the updated program.
If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. The DSB instruction ensures subsequent instruction execution uses the updated memory map.
When an exception priority has to change when the exception is pending or active, use DSB instructions after the change. The change then takes effect on completion of the DSB instruction.
For more information on the memory barrier instructions, see the Cortex-M4 instruction set chapter in the Arm Cortex-M4 Devices Generic User Guide.