SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The COUNT0 field in the EPIBAUD register must be configured to set the main transaction rate based on what the slave device can support (including wiring considerations). The main control transitions are normally 1/2 the baud rate (COUNT0 = 1) because the EPI block forces data versus control to change on alternating clocks. When using dual chip selects, each chip select can access the bus using differing baud rates by setting the CSBAUD bit in the EPIHBnCFG2 register. In this case, the COUNT0 field controls the CS0n transactions, and the COUNT1 field controls the CS1n transactions. When using quad chip select mode, the COUNT0 bit field of the EPIBAUD2 register controls the baud rate of CS2n and the COUNT1 bit field is programmed to control the baud rate of CS3n.
Additionally, the Host-Bus mode provides read and write wait states for the data portion to support different classes of device. These wait states stretch the data period (hold the rising edge of data strobe) and may be used in all four sub-modes. The wait states are set using the WRWS and RDWS bits in the EPI Host-Bus n Configuration (EPIHBnCFGn) register. The WRWS and RDWS bits are enhanced with more precision by WRWSM and RDWSM bits in the EPIHBnTIMEn registers. Note none of the wait state configuration bits can be set concurrently with the BURST bit in the same EPIHBnCFGn register. See Table 16-10 for programming information.
| RDWS or WRWS Encoding in EPIHBnCFGn Register | RDWSM or WRWSM Encoding in EPIHBnTIMEn Registers | Data Phase Wait States |
|---|---|---|
| 0x0 | 1 | 1 EPI clock cycle |
| 0x0 | 0 | 2 EPI clock cycles |
| 0x1 | 1 | 3 EPI clock cycles |
| 0x1 | 0 | 4 EPI clock cycles |
| 0x2 | 1 | 5 EPI clock cycles |
| 0x2 | 0 | 6 EPI clock cycles |
| 0x3 | 1 | 7 EPI clock cycles |
| 0x3 | 0 | 8 EPI clock cycles |
The CAPWIDTH bit in EPIHBnTIMEn registers controls the delay between Host-Bus transfers. When the CSBAUD bit is set and multiple chip selects have been configured in the EPIHBnCFG2 registers, delay takes an additional clock cycle to adjust the clock rate of different chip selects.
Word read and write transactions can be enhanced through the enabling of the BURST bit in the EPIHB16CFGn registers.