SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Standard, fast, and fast plus modes are selected using a value in the I2C Master Timer Period (I2CMTPR) register that results in an SCL frequency of 100 kbps for standard mode, 400 kbps for fast mode, or 1 Mbps for fast mode plus.
The I2C clock rate is determined by the parameters CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP where:
TIMER_PRD is the programmed value in the I2CMTPR register (see Section 19.5.4). This value is determined by replacing the known variables in Equation 61 and solving for TIMER_PRD. The I2C clock period is calculated as follows:
For example:
Yields an SCL frequency of: 1 / SCL_PERIOD = 338 KHz
Table 19-1 lists examples of the timer periods that should be used to generate standard, fast mode, and fast mode plus SCL frequencies based on various system clock frequencies.
| System Clock | Standard Mode | Fast Mode | Fast Mode Plus | |||
|---|---|---|---|---|---|---|
| Timer Period | Data Rate | Timer Period | Data Rate | Timer Period | Data Rate | |
| 4 MHz | 0x01 | 100 kbps | -– | – | – | – |
| 6 MHz | 0x02 | 100 kbps | – | – | – | – |
| 12.5 MHz | 0x06 | 89 kbps | 0x01 | 312 kbps | – | – |
| 16.7 MHz | 0x08 | 93 kbps | 0x02 | 278 kbps | – | – |
| 20 MHz | 0x09 | 100 kbps | 0x02 | 333 kbps | – | – |
| 25 MHz | 0x0C | 96.2 kbps | 0x03 | 312 kbps | – | – |
| 33 MHz | 0x10 | 97.1 kbps | 0x04 | 330 kbps | – | – |
| 40 MHz | 0x13 | 100 kbps | 0x04 | 400 kbps | 0x01 | 1000 kbps |
| 50 MHz | 0x18 | 100 kbps | 0x06 | 357 kbps | 0x02 | 833 kbps |
| 80 MHz | 0x27 | 100 kbps | 0x09 | 400 kbps | 0x03 | 1000 kbps |
| 100 MHz | 0x31 | 100 kbps | 0x0C | 385 kbps | 0x04 | 1000 kbps |
| 120 MHz | 0x3B | 100 kbps | 0xE | 400 kbps | 0x5 | 1000 kbps |