| 31-18 |
RESERVED |
R |
0x0 |
|
| 17 |
LDOSME |
R |
0x1 |
LDO Sleep Mode Enable
0x0 = The LDOSM bit of the DSLPPWRCFG register is ignored.
0x1 = The LDOSM bit of the DSLPPWRCFG register can be set to place the LDO in a low-power mode when deep-sleep mode is entered.
|
| 16 |
TSPDE |
R |
0x1 |
Temp Sense Power Down Enable.
This bit allows the internal temperature sensor in the ADC to be powered off in deep-sleep mode.
0x0 = The TSPD bit of the DSLPPWRCFG register is ignored.
0x1 = The TSPD bit of the DSLPPWRCFG register can be set to power off the temperature sensor in deep-sleep mode.
|
| 15-13 |
RESERVED |
R |
0x0 |
|
| 12 |
PIOSCPDE |
R |
0x1 |
PIOSC Power Down Present.
This bit determines whether the PIOSCPD bit in the DSCLKCFG register can be set to power down the PIOSC in deep-sleep mode.
0x0 = The status of the PIOSCPD bit is ignored.
0x1 = The PIOSCPD bit can be set to power down the PIOSC in deep-sleep mode.
|
| 11 |
SRAMSM |
R |
0x1 |
SRAM Sleep/Deep-Sleep Standby Mode Present.
This bit determines whether the SRAMPM field in the SLPPWRCFG and DSLPPWRCFG registers can be configured to put the SRAM into standby mode while in sleep or deep-sleep mode.
0x0 = A value of 0x1 in the SRAMPM fields is ignored.
0x1 = The SRAMPM fields can be configured to put the SRAM into standby mode while in sleep or deep-sleep mode.
|
| 10 |
SRAMLPM |
R |
0x1 |
SRAM Sleep/Deep-Sleep Low Power Mode Present.
This bit determines whether the SRAMPM field in the SLPPWRCFG and DSLPPWRCFG registers can be configured to put the SRAM into low-power mode while in sleep or deep-sleep mode.
0x0 = A value of 0x3 in the SRAMPM fields is ignored.
0x1 = The SRAMPM fields can be configured to put the SRAM into low-power mode while in sleep or deep-sleep mode.
|
| 9 |
RESERVED |
R |
0x0 |
|
| 8 |
FLASHLPM |
R |
0x1 |
Flash Memory Sleep/Deep-Sleep Low Power Mode Present.
This bit determines whether the FLASHPM field in the SLPPWRCFG and DSLPPWRCFG registers can be configured to put the flash memory into low-power mode while in sleep or deep-sleep mode.
0x0 = A value of 0x2 in the FLASHPM fields is ignored.
0x1 = The FLASHPM fields can be configured to put the flash memory into low-power mode while in sleep or deep-sleep mode.
|
| 7-6 |
RESERVED |
R |
0x0 |
|
| 5 |
LDOSEQ |
R |
0x1 |
Automatic LDO Sequence Control Present.
This bit indicates that the ability to sequence the LDO output voltage is available during sleep and deep-sleep modes.
0x0 = Software cannot set the VADJEN bit in the LDOSPCTL and LDODPCTL registers.
0x1 = Software can set the VADJEN bit in the LDOSPCTL and LDODPCTL registers.
|
| 4-1 |
RESERVED |
R |
0x0 |
|
| 0 |
FPU |
R |
0x1 |
FPU Present.
This bit indicates if the FPU is present in the Cortex -M4 core.
0x0 = FPU is not present.
0x1 = FPU is present.
|