SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state may be entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG module and associated registers are reset to their default values. This procedure should be performed to initialize the JTAG controller. The JTAG Test Access Port state machine can be seen in its entirety in Figure 3-2.
By default, the internal pullup resistor on the TMS pin is enabled after reset. Changes to the pullup resistor settings on GPIO Port C should ensure that the internal pullup resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost (see Section 17.5.15).