SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Figure 23-2 shows the TI synchronous serial frame format for a single transmitted frame.
In this mode, SSInClk and SSInFss are forced Low, and the transmit data line SSInDAT0/SSInTX is in a tristate condition whenever the QSSI is idle. Once the bottom entry of the transmit FIFO contains data, SSInFss is pulsed High for one SSInClk period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSInClk, the MSB of the 4- to 16-bit data frame is shifted out on the SSInDAT0 and SSInTX pins. Likewise, the MSB of the received data is shifted onto the SSInDAT1 and SSInRX pins by the off-chip serial slave device.
Both the QSSI and the off-chip serial slave device then clock each data bit into their serial shifter on each falling edge of SSInClk. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSInClk after the LSB has been latched.
Figure 23-3 shows the TI synchronous serial frame format when back-to-back frames are transmitted.