SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The TX FIFO can be flushed by setting the FTF bit in the EMACDMAOPMODE register. The flush operation is immediate and the TX/RX Controller clears the TX FIFO and the corresponding pointers to the initial state even if it is in the middle of transferring a frame to the MAC. The data which is already accepted by the MAC transmitter is not flushed. This data is scheduled for transmission and results in an underflow event because the TX FIFO did not complete the transfer or the rest of the frame. As in all underflow conditions, a runt frame is transmitted and observed on the line. The status of such a frame is marked with both underflow and frame flush events in the Transmit Descriptor 0 (TDES0) word.
The TX/RX Controller also stops accepting any data from the DMA during the flush operation. It generates and transfers Transmit Status Words to the application for the frames that are flushed inside the FIFO, including partial frames. Frames that are completely flushed in the TX/RX Controller are identified by setting the Flush Status (FF) bit in the Transmit Descriptor 0 (TDES0) word. The TX/RX Controller completes the flush operation when the DMA accepts all of the status words for the frames that were flushed and then clears the TX FIFO Flush control (FTF) bit in the EMACDMAOPMODE register. At this point, the TX/RX Controller starts accepting new frames from the DMA.