SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280
Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284
Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288
Interrupt 96- 113 Clear Pending (UNPEND3), offset 0x28C
NOTE
This register can only be accessed from privileged mode.
The UNPENDn registers show which interrupts are pending and remove the pending state from interrupts. Bit 0 of UNPEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of UNPEND1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of UNPEND2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of UNPEND3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 113.
See for interrupt assignments.
UNPENDn is shown in Figure 2-9 and described in Table 2-19.
Return to Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT | |||||||||||||||||||||||||||||||
R/W-0x0 | |||||||||||||||||||||||||||||||