SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
When the USB module uses the integrated USB PHY, the MOSC must be the clock source, either with or without the PLL, and the system clock must be at least 30 MHz. In addition, only integer divisors should be used to achieve the 60-MHz USB clock source. Fractional divisors may increase jitter and compromise USB function. Program the CLKDIV bit field in the USB Clock Control (USBCC) register to specify the divisor used to reduce the PLL VCO output to the 60-MHz clock source required for the serialization and deserialization module of the USB controller.
In ULPI mode, if the clock source to the USB is internal, the USB0CLK pin is an output to the external ULPI PHY. If the USB clock source is external, the USB0CLK pin functions as an input from the external ULPI PHY.