27.5.35 USBCSRH0 Register (Offset = 0x103) [reset = 0x0]
USB Control and Status Endpoint 0 High (USBCSRH0), offset 0x103
OTG A / Host
OTG B / Device
USBSR0H is an 8-bit register that provides control and status bits for endpoint 0.
USBCSRH0 for OTG A / Host is shown in Figure 27-41 and described in Table 27-46.
USBCSRH0 for OTG B / Device is shown in Figure 27-42 and described in Table 27-47.
Return to Summary Table.
Figure 27-41 USBCSRH0 Register (OTG A / Host)
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DISPING |
DTWE |
DT |
FLUSH |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 27-46 USBCSRH0 Register Field Descriptions (OTG A / Host)
| Bit |
Field |
Type |
Reset |
Description |
| 7-4 |
RESERVED |
R |
0x0 |
|
| 3 |
DISPING |
R/W |
0x0 |
PING Disable.
This bit is available for devices that do not respond to PING.
0x0 = PING token issues enabled.
0x1 = PING tokens are not issued in data and status phases of high-speed control transfer.
|
| 2 |
DTWE |
R/W |
0x0 |
Data Toggle Write Enable.
This bit is automatically cleared once the new value is written.
0x0 = The DT bit cannot be written.
0x1 = Enables the current state of the endpoint 0 data toggle to be written (see DT bit).
|
| 1 |
DT |
R/W |
0x0 |
Data Toggle.
When read, this bit indicates the current state of the endpoint 0 data toggle.
If DTWE is set, this bit may be written with the required setting of the data toggle.
If DTWE is Low, this bit cannot be written.
Care should be taken when writing to this bit as it should only be changed to RESET USB endpoint 0. |
| 0 |
FLUSH |
R/W |
0x0 |
Flush FIFO.
This bit is automatically cleared after the flush is performed.
This bit should only be set when TXRDY is clear and RXRDY is set.
At other times, it may cause data to be corrupted.
0x0 = No effect.
0x1 = Flushes the next packet to be transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset and the TXRDY / RXRDY bit is cleared.
|
Figure 27-42 USBCSRH0 Register (OTG B / Device)
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
FLUSH |
| R-0x0 |
R/W-0x0 |
|
Table 27-47 USBCSRH0 Register Field Descriptions (OTG B / Device)
| Bit |
Field |
Type |
Reset |
Description |
| 7-1 |
RESERVED |
R |
0x0 |
|
| 0 |
FLUSH |
R/W |
0x0 |
Flush FIFO.
This bit is automatically cleared after the flush is performed.
This bit should only be set when TXRDY is clear and RXRDY is set.
At other times, it may cause data to be corrupted.
0x0 = No effect.
0x1 = Flushes the next packet to be transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset and the TXRDY / RXRDY bit is cleared.
|