SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB Device RESUME Interrupt Mask (USBDRIM)
OTG A / Host
OTG B / Device
The USBDRIM 32-bit register is the masked interrupt status register. On a read, this register gives the current value of the mask on the corresponding interrupt. Setting a bit sets the mask, preventing the interrupt from being signaled to the interrupt controller. Clearing a bit clears the corresponding mask, enabling the interrupt to be sent to the interrupt controller.
USBDRIM is shown in Figure 27-83 and described in Table 27-90.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESUME | ||||||
R-0x0 | R/W-0x0 | ||||||