SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB FIFO Endpoint 0 (USBFIFO0), offset 0x020
USB FIFO Endpoint 1 (USBFIFO1), offset 0x024
USB FIFO Endpoint 2 (USBFIFO2), offset 0x028
USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C
USB FIFO Endpoint 4 (USBFIFO4), offset 0x030
USB FIFO Endpoint 5 (USBFIFO5), offset 0x034
USB FIFO Endpoint 6 (USBFIFO6), offset 0x038
USB FIFO Endpoint 7 (USBFIFO7), offset 0x03C
OTG A / Host
OTG B / Device
These 32-bit registers provide an address for CPU access to the FIFOs for each endpoint. Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint. Reading from these addresses unloads data from the Receive FIFO for the corresponding endpoint.
Transfers to and from FIFOs may be 8-bit, 16-bit or 32-bit as required, and any combination of accesses is allowed provided the data accessed is contiguous. All transfers associated with one packet must be of the same width so that the data is consistently byte-, halfword- or word-aligned. However, the last transfer may contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word transfer.
Depending on the size of the FIFO and the expected maximum packet size, the FIFOs support either single-packet or double-packet buffering (see Section 27.3.1.3.1). Burst writing of multiple packets is not supported as flags must be set after each packet is written.
Following a STALL response or a transmit error on endpoint 1 to 7, the associated FIFO is completely flushed.
USBFIFOn is shown in Figure 27-17 and described in Table 27-22.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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