SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB VBUS Droop Control Interrupt Status and Clear (USBVDCISC)
OTG A / Host
This 32-bit register specifies the masked interrupt status of the VBUS droop and provides a method to clear the interrupt state.
USBVDCISC is shown in Figure 27-89 and described in Table 27-96.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0x0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VD | ||||||||||||||
R-0x0 | R/W1C-0x0 | ||||||||||||||