SLAU776A May   2018  – December 2023 ADC12DL2500 , ADC12DL3200

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1.     Related Documentation
      1.      Technical Reference Documents
      2.      TSW14DL3200EVM Operation
  5. 2Equipment
    1. 2.1 Evaluation Board Feature Identification Summary
    2. 2.2 Required Equipment
  6. 3Setup Procedure
    1. 3.1  Install the High Speed Data Converter (HSDC) Pro Software
    2. 3.2  Install the Configuration GUI Software
    3. 3.3  Connect the EVM and TSW14DL3200EVM
    4. 3.4  Connect the Power Supplies to the Boards (Power Off)
    5. 3.5  Connect the Signal Generators to the EVM (*RF Outputs Disabled Until Directed)
      1. 3.5.1 If External Clocking is Used (Optional)
    6. 3.6  Turn On the TSW14DL3200EVM Power and Connect to the PC
    7. 3.7  Turn On the ADC12DLXX00EVM 5-V Power Supply and Connect to the PC
    8. 3.8  Turn On the Signal Generator RF Outputs
    9. 3.9  Open the ADC12DLXX00EVM GUI and Program the ADC and Clocks
    10. 3.10 Calibrate the ADC Device on the EVM
    11. 3.11 Open the HSDC Software and Load the FPGA Image to the TSW14DL3200EVM
    12. 3.12 Capture Data Using the HSDC Pro Software
  7. 4Device Configuration
    1. 4.1 Tab Organization
    2. 4.2 Low-Level Control
  8.   A Troubleshooting the ADC12DL3200EVM
  9.   B Optional ADC12DL3200EVM Configurations
  10.   C Revision History

B Optional ADC12DL3200EVM Configurations

This appendix provides settings for modifying the EVM for optional clocking support.

The LMK04828 provides a buffered copy of the onboard 100-MHz VCXO to the LMX2582. When the optional 10-MHz reference clock is connected, the 100-MHz VCXO output is frequency locked to the 10-MHz reference. This process enables coherent sampling of the analog input signal. The EVM can be configured to use an external ADC clock with the following steps (see Figure 6-1):

  1. Modify the hardware:
    1. Remove C114 and C124, populate C24 and C25.
  2. Connect the signal generators:
    1. Connect the 10-MHz reference from Sig Gen 1 to Sig Gen 2.
    2. Configure Sig Gen 2 to use the 10-MHz reference input from Sig Gen 1.
    3. Sig Gen 1 connects to DEVCLK (J12). Set to the generator frequency to the desired FCLK. Set output level to +9 dBm.
    4. Sig Gen 2 connects to the desired analog input with output level at 0 dBm for the starting point.
  3. Program the GUI:
    1. In the EVM tab, set the clock source to External.
    2. Enter the Sampling Frequency (FCLK) in step 2b.

GUID-295FCCAD-3159-4573-9242-E9BE5A04BAB9-low.png Figure B-1 External CLK Configuration

The ADC12DL3200EVM includes a reference clock input (CLKIN0) that allows the user to sync the LMK04828 to an external 10-MHz reference allowing for coherent sampling

The LMX2582 and LMK04828 may be reconfigured to exercise more features, but this EVM is not intended to be a full evaluation platform for these devices. For a full evaluation platform, see the LMK04828 tool folder and LMX2582 tool folder.