2 Functionality

The TSW1418EVM has a single, industry-standard FMC connector that interfaces directly with TI non-JESD204B/C ADC EVMs using FMC connectors. When used with an ADC EVM, LVDS or CMOS data is captured and formatted by a Xilinx Artix® 7 XC7A100T field-programmable gate array (FPGA). The data is then stored into the FPGA internal memory, enabling the TSW1418EVM to store up to 64K 16-bit data samples. To acquire data on a host PC, the FPGA transmits the data on a high-speed, 8-bit parallel interface. An onboard USB-to-parallel converter bridges the FPGA interface to the host PC and GUI.

The major features of the TSW1418EVM are:

• Entry-level, low-cost data capture platform
• USB powered
• 21 differential LVDS pairs with speeds up to 950Mbps dual data rate (DDR)
• 64K of 16-bit samples of internal FPGA memory
• Supports 1.8-V CMOS IO standard
• Onboard FTDI USB device for JTAG and SPI to the FPGA
• Spare clocking and general-purpose I/O available through FMC port or SMAs
• Supported by TI HSDC PRO software
• FPGA firmware developed with Xilinx Vivado® v17.2
• Digilent JTAGHS2 FPGA PROGRAMMING CABLE, PN: 410-249

Figure 2-1 shows a block diagram of the TSW1418EVM.

Figure 2-1 TSW1418EVM Block Diagram