SLAU789A November   2023  – November 2023

 

  1.   1
  2.   TSW1418EVM High-Speed Data Capture Card
  3.   Trademarks
  4. 1Introduction
    1. 1.1 REACH Compliance
  5. 2Functionality
    1. 2.1 ADC EVM Data Capture
  6. 3Hardware
    1. 3.1 Power Connections
    2. 3.2 Switches, Push-Buttons, Jumpers, and LEDs
      1. 3.2.1 Switches and Push-Buttons
      2. 3.2.2 Jumpers
      3. 3.2.3 LEDs
        1. 3.2.3.1 Power LED
        2. 3.2.3.2 Status LEDs
    3. 3.3 Connectors
      1. 3.3.1 SMA Connectors
      2. 3.3.2 FPGA Mezzanine Card (FMC) Connector
      3. 3.3.3 JTAG Connector
      4. 3.3.4 USB I/O Connection
  7. 4Software
    1. 4.1 Installation Instructions
    2. 4.2 USB Interface and Drivers
    3. 4.3 Downloading Firmware
  8. 5Revision History

3.3.2 FPGA Mezzanine Card (FMC) Connector

The TSW1418EVM has one connector to allow for the direct plug in of new TI LVDS and CMOS interface ADC EVMs. The FMC connector, J12, provides the interface between the TSW1418EVM and the ADC EVM under test.

In addition to several clocks and the 21 LVDS signal pairs or 42 CMOS single-ended signals (depending on how the FPGA is configured), there are several CMOS single-ended signals and spare LVDS differential signals are connected between the FMC and FPGA. In the future, these signals can allow the HSDC Pro GUI to control the SPI serial programming of ADC EVMs that support this feature. The connector pinout description is shown in Table 3-5.

Table 3-5 FMC Connector Descriptions
FMC Signal Name FMC Pin Description
FPGA_REFCLK_P/N G6 and G7 Optional input sample clock from ADC EVM (LVDS or CMOS)
FPGA_CLK_P/N H4 and H5 Optional output sample clock to ADC EVM (LVDS or CMOS)
FCLK_P/N E2 and E3 Input frame clock from ADC EVM (LVDS or CMOS)
DCLKIN_FPGA_P/N K16 and K17 Output data clock to ADC EVM (LVDS or CMOS)
DCLK_P/N F4 and F5 Input data clock from ADC EVM (LVDS or CMOS)
HA05_P/N E6 and E7 Input data from ADC EVM (LVDS or CMOS)
HA09_P/N E9 and E10 Input data from ADC EVM (LVDS or CMOS)
HA013_P/N E12 and E13 Input data from ADC EVM (LVDS or CMOS)
HA016_P/N E15 and E16 Input data from ADC EVM (LVDS or CMOS)
HA20_P/N E18 and E19 Input data from ADC EVM (LVDS or CMOS)
HA04_P/N F7 and F8 Input data from ADC EVM (LVDS or CMOS)
HA08_P/N F10 and F11 Input data from ADC EVM (LVDS or CMOS)
HA12_P/N F13 and F14 Input data from ADC EVM (LVDS or CMOS)
HA15_P/N F16 and F17 Input data from ADC EVM (LVDS or CMOS)
HA19_P/N F19 and F20 Input data from ADC EVM (LVDS or CMOS)
HA03_P/N J6 and J7 Input data from ADC EVM (LVDS or CMOS)
HA07_P/N J9 and J10 Input data from ADC EVM (LVDS or CMOS)
HA11_P/N J12 and J13 Input data from ADC EVM (LVDS or CMOS)
HA14_P/N J15 and J16 Input data from ADC EVM (LVDS or CMOS)
HA18_P/N J18 and J19 Input data from ADC EVM (LVDS or CMOS)
HA22_P/N J21 and J22 Input data from ADC EVM (LVDS or CMOS)
HA02_P/N K7 and K8 Input data from ADC EVM (LVDS or CMOS)
HA06_P/N K10 and K11 Input data from ADC EVM (LVDS or CMOS)
HA10_P/N K13 and K14 Input data from ADC EVM (LVDS or CMOS)
HA21_P/N K19 and K20 Input data from ADC EVM (LVDS or CMOS)
HA23_P/N K22 and K23 Input data from ADC EVM (LVDS or CMOS)
FMC_GPIO_0 G21 General purpose I/O
FMC_GPIO_1 G22 General purpose I/O
FMC_GPIO_2 G24 General purpose I/O
FMC_GPIO_3 G25 General purpose I/O
FMC_SCLK G27 ADC clock (SCLK) for SPI from FMC connector
FMC_SEN G28 ADC enable (SEN) for SPI from FMC connector
FMC_POCI G30 ADC input data (POCI) for SPI from FMC connector
FMC_PICO G31 ADC output data (PICO) for SPI from FMC connector
FMC_PICO_EN G33 FPGA output data enable for SPI from FMC connector
FMC_SCL G34 I2C enable from FMC connector
FMC_SDA_OUT G36 I2C data out from FMC connector
FMC_SDA_IN G37 I2C data in from FMC connector