SLAU858A november   2021  – june 2023

 

  1.   1
  2.   AFE881H1 Evaluation Module
  3.   Trademarks
  4. 1Overview
    1. 1.1 Kit Contents
    2. 1.2 Related Documentation From Texas Instruments
  5. 2USB2ANY Interface Adapter
    1. 2.1 Signal Definitions for J10
    2. 2.2 USB2ANY Theory of Operation
  6. 3EVM Hardware Overview
    1. 3.1 Electrostatic Discharge Caution
    2. 3.2 EVM Block Diagram
    3. 3.3 EVM Jumper Summary
    4. 3.4 Terminal and Pin Definitions
    5. 3.5 Connecting the USB2ANY
    6. 3.6 Connecting the USB Cable to the USB2ANY Interface Adapter
    7. 3.7 Optional EVM Operations
      1. 3.7.1 Power Configuration
      2. 3.7.2 External SPI and UART Controllers
  7. 4Software Overview
    1. 4.1 Software Installation
    2. 4.2 Launching the Software
    3. 4.3 Software Features
      1. 4.3.1 AFE881H1 Register Page
      2. 4.3.2 High Level Configuration Page
      3. 4.3.3 Using the Python Scripting Tool
  8. 5Schematics, PCB Layout, and Bill of Materials
    1. 5.1 Board Schematic
    2. 5.2 PCB Components Layout
    3. 5.3 Bill of Materials
  9. 6Revision History

3.4 Terminal and Pin Definitions

Table 3-2 shows the EVM terminal and pin definitions, allowing the user to operate and connect the device to optional power settings and other input and output signals.

Table 3-2 AFE881H1EVM Terminal and Pin Definitions
Terminal or Pin Name Function

J1

VDD

Shunt 1-2: Connect VDD to PVDD for use when VDD = PVDD = 1.8 V

Open 1-2: Disconnects VDD when PVDD > 1.8 V

J2

PVDD

Banana Jack: Optional for external PVDD

J3

3p3V

Shunt 1-2: Connect PVDD to USB2ANY 3.3-V supply

Shunt 3-4: Connect IOVDD to USB2ANY 3.3-V supply

J4

GND

Banana Jack: Optional for external GND

J5

VREFIO

Shunt 1-2: Connect REF3312 to VREFIO for external reference

Open 1-2: Open for device internal reference

J6

IOVDD

Shunt 1-2: Connect IOVDD to power

J7

REF EN

Shunt 1-2: Enable device internal reference

Shunt 2-3: Disable device internal reference

J8

UARTIN

Shunt 1-2: Connect UARTIN to device from USB2ANY through voltage level shifter
J9 SPI Conn Pin 1: RESET
Pin 3: SCLK

Pin 5: SDI
Pin 7: CS
Pin 9: SDO
Pin 2, 4, 6, 8, 10: GND
Ground connections are on the interior side of the board. Signals are on the edge side of the board.

J10

USB2ANY

30-pin ribbon cable connection, see Table 2-1
J11 ADC

Terminal 1: AIN0

Terminal 2: GND

Terminal 3: AIN1
J12 UART Conn Pin 1: UART_IN
Pin 3: UART_OUT
Pin 5: RTS
Pin 7: CD
Pin 9: ALARM
Pin 2, 4, 6, 8, 10: GND
Ground connections are on the interior side of the board. Signals are on the edge side of the board.
J13 POL_SEL

Shunt 1-2: Pull up to PVDD

Shunt 2-3: Pull down to GND

Open: Connection to AIN1 terminal of J11

J14

RES_LOAD

Shunt 1-2: Connect 10-kΩ load to VOUT

J15

VOUT

Terminal 1: GND

Terminal 2: VOUT

J16

CLK_OUT

Pin 1: CLK_OUT

Pin 2: GND

J17

CAP_LOAD

Shunt 1-2: Connect 150-pF load to VOUT

J18

IOVDD

Banana Jack: Optional for external IOVDD

J19, J20

FILT_SEL

Shunt 1-2: HART IN terminal internal filter selected

Shunt 2-3: HART IN terminal external filter selected

J21

HART_IN

Terminal 1: GND

Terminal 2: HART input

J22

HART_OUT

Terminal 1: GND

Terminal 2: HART output

Figure 3-3 shows the terminal and pin locations on the EVM.

GUID-20210619-CA0I-KF5R-GLM0-WBKLT8JJJH6L-low.svg Figure 3-3 Terminal and Pin Locations for the AFE881H1EVM