SLAU880C December   2022  – May 2024 ULC1001

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  5. 2Introduction
  6. 3Getting Started
    1. 3.1 Evaluation Kit Contents
    2. 3.2 Connection Procedure
    3. 3.3 GUI Setup
  7. 4System Overview
    1. 4.1 System ISR Period
    2. 4.2 System Drive Voltage
    3. 4.3 System Calibration
      1. 4.3.1 DC Bias Calibration
      2. 4.3.2 Temperature Calibration
      3. 4.3.3 Auto Sense Calibration
      4. 4.3.4 Cleaning and Power Calibration
    4. 4.4 System Cleaning
    5. 4.5 System Diagnostics
  8. 5GUI Overview
    1. 5.1 GUI Top Level Layout
      1. 5.1.1 North Pane
      2. 5.1.2 South Pane
      3. 5.1.3 Center Pane
    2. 5.2 High Level Page
      1. 5.2.1 Burst Parameters
      2. 5.2.2 Calibration Settings
        1. 5.2.2.1 Voltage and Current Sense Circuitry
      3. 5.2.3 Cleaning Mode Settings
        1. 5.2.3.1 Auto-Cleaning
        2. 5.2.3.2 Water Cleaning
        3. 5.2.3.3 Deice Cleaning
        4. 5.2.3.4 Mud Cleaning Mode
      4. 5.2.4 Power and Diagnostic Settings
    3. 5.3 Register Map Page
    4. 5.4 I2C Configuration Page
    5. 5.5 GUI Functions
      1. 5.5.1 Monitor Communication Status
      2. 5.5.2 Load and Save Configuration Files
        1. 5.5.2.1 MSP430 Firmware Programming
      3. 5.5.3 Re-initialize System
      4. 5.5.4 Fault and Flag Monitoring and Clearing
      5. 5.5.5 Run Calibration
      6. 5.5.6 Run Cleaning Modes
      7. 5.5.7 Run Diagnostic Mode
      8. 5.5.8 Run Abort
      9. 5.5.9 Script Recording
  9. 6Hardware Design Files
    1. 6.1 Schematics
    2. 6.2 PCB Layouts
    3. 6.3 Bill of Materials (BOM)
  10. 7Revision History

4.1 System ISR Period

The ULC1001 can be configured to run at different ISR periods to accommodate different types of Lens Cover Systems. The ISR period is inversely related to the ADC sample rate, Fs, and inversely related to the minimum frequency step size for active bursts, 512. The ISR period can be adjusted by changing the hardware register ULC_RX_mode_cfg, which must be equal to the software register USER_Params_fs_Hz_Q9. The hardware register sets the PLL Clock divider ratio used to configure Fs. The software register is used to configure the algorithm settings for processing current and voltage sense data. The relationship is ISR period = 512/Fs, where 512 is the USER_Params_blockSize.

The default ISR period is 512/500 ksps = 1.024ms. All the timings in the GUI, such as duration or delay, are scaled to the ISR period. The GUI updates timings accordingly when Fs is changed. Recommended sample rates are 400 ksps and 500 ksps.

When the ADC sample rate is changed, the Delta_Freq setting for all active bursts is also changed. The relationship is Delta_Freq = Fs/N, where N is the number of samples. When driving high-Q transducers, the Delta_Freq can be minimized by setting the minimum Fs and maximum N. Valid number of samples are 512, 1024, and 2048.

To achieve a lower sample rate and ultimately a lower minimum output frequency, enable manual clocking mode. The valid PLL Clocks for manual clocking mode and 40MHz, 60MHz, and 80MHz. When in manual clock mode, all burst timings and active mode burst frequencies must be scaled appropriately. Refer to the ULC1001-Q1 data sheet for an example of changing the PLL Clock to 80MHz and adjusting all dependent registers.

Table 4-1 ISR Configuration Settings
ULC_SAR_SAMP_RATESSets the internal ADC sample rate. Must also set USER_Params_fs_Hz_Q9 to the same value.
USER_Params_numSamplesSets the number of samples. Must be set equal to USER_Params_blockSize*USER_Params_numStages, where USER_Params_blockSize = 512 (Do not change). GUI changes USER_Params_numStages to the valid settings of 1, 2, 4.