The Arm Cortex-M0+ processor instructions operate on registers in the CPU register file. The processor contains a register file consisting of 16 standard registers and 3 special registers as
shown in Figure 3-2.
General Purpose Registers (R0-R12)
The processor provides 13 general purpose registers, R0-R12, for operating on data. Registers R0 to R7 (low registers) are accessible by all instructions which specify a general purpose
register. Registers R8 to R12 (high registers) are not accessible by 16-bit instructions but are accessible by any 32-bit instructions which specify a general purpose register.
Stack Pointer Register (R13)
The stack pointer is contained in R13,
and can contain the main stack pointer (MSP) or the process stack pointer (PSP) .
When the processor is running in handler mode, the main stack pointer (MSP) is
always used. When the processor is running in thread mode, the MSP or the process
stack pointer (PSP) can be used, depending on the configuration of the SPSEL bit in
the CONTROL register.
After a CPURST, the processor automatically and unconditionally fetches the default stack pointer from the first address of main flash (0x0000.0000) as the main stack pointer (MSP).
Link Register (R14)
R14 serves as the link register and contains the return value of function calls as well as exceptions. The link register must be set before being used as it is not reset to any known value. It
is accessible in privileged and unprivileged mode.
Program Counter Register (R15)
The program counter register (R15) contains the address of the next instruction to be executed. The PC is accessible in privileged and unprivileged mode.
After a CPURST, the processor automatically and unconditionally fetches the default PC from the second word of main flash (0x0000.0004).
Special Registers
Special registers include the program status register (PSR), the interrupt mask register (PRIMASK), and the control register (CONTROL). Special registers are typically accessed by using the CPS,
MRS, and MSR system instructions.
- Program Status Register (PSR): The PSR is a combination of the application status (APSR), interrupt status (IPSR), and execution status (EPSR) registers. Application software can
access the PSR with MRS and MSR instructions, accessing either the complete PSR or a combination of one or more registers, with some restrictions. The PSR registers can be accessed with MRS and MSR instructions using the mnemonics given
in Table 3-1.
- The application status register (APSR) contains the N, Z, C, and V flags which are used by the processor to evaluate conditional branch instructions. These bits are located in BIT31,
BIT30, BIT29, and BIT28 of the PSR, respectively.
- The interrupt status register (IPSR) reports the current exception number for a currently executing exception when in handler mode. In thread mode it reads as zero. The processor
ignores writes to this register. The exception number field is presented in from BIT0 to BIT5 of the PSR.
- The execution status register (EPSR) contains the T bit (BIT24), which defines whether the processor is in Thumb state. This bit cannot be read or written by software, but it is used by
the processor.
- Interrupt Mask Register (PRIMASK): BIT0 of the PRIMASK register (PM) can be used to mask all interrupts to the processor which have configurable priority (see Section 3.3). This can be thought of as a global peripheral interrupt mask control. The processor ignores unprivileged writes to PRIMASK. Clearing PM to 0 enables interrupts. Setting
PM to 1 disables interrupts. The CPS instruction can be used to change the PM bit value in the PRIMASK register.
- Control Register (CONTROL): The control register can be used to define whether code executing in thread mode is privileged or unprivileged by clearing or setting the nPRIV bit
(BIT0), respectively. It can also be used to select the stack pointer used in R13 as either the main stack pointer (MSP) or process stack pointer (PSP) by clearing or setting the SPSEL bit (BIT1), respectively. A CPURST clears the
CONTROL register to zero. The processor ignores unprivileged writes to the CONTROL register. The SPSEL stack pointer selection bit is updated by the processor automatically when entering and returning from exceptions. Note that software
must implement an ISB barrier instruction after writing to CONTROL to ensure that any changes take effect before the next application instruction is executed by the processor.
Table 3-1 Program Status Register (PSR) Access Mnemonics
Mnemonic |
Subregisters Included |
APSR |
APSR |
IPSR |
IPSR |
EPSR |
EPSR |
IAPSR |
IPSR and APSR |
EAPSR |
EPSR and APSR |
XPSR |
APSR, IPSR, EPSR |
IEPSR |
IPSR and EPSR |