SLAU893B October   2023  – July 2024 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
    5. 1.5 NONMAIN_C1103_C1104 Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 Peripheral Power Enable Control
        1. 2.2.6.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.1.1 SYSOSC FCL in Internal Resistor Mode
          2. 2.3.1.2.2 Disabling SYSOSC
        3. 2.3.1.3 LFCLK_IN (Digital Clock)
        4. 2.3.1.4 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1 MCLK (Main Clock) Tree
        2. 2.3.2.2 CPUCLK (Processor Clock)
        3. 2.3.2.3 ULPCLK (Low-Power Clock)
        4. 2.3.2.4 MFCLK (Middle Frequency Clock)
        5. 2.3.2.5 LFCLK (Low-Frequency Clock)
        6. 2.3.2.6 ADCCLK (ADC Sample Period Clock)
        7. 2.3.2.7 External Clock Output (CLK_OUT)
        8. 2.3.2.8 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 MCLK Monitor
        2. 2.3.4.2 Startup Monitors
          1. 2.3.4.2.1 LFOSC Startup Monitor
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Shutdown Mode Handling
      7. 2.4.7  Configuration Lockout
      8. 2.4.8  System Status
      9. 2.4.9  Error Handling
      10. 2.4.10 SYSCTL Events
        1. 2.4.10.1 CPU Interrupt Event (CPU_INT)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Optimizing for Lowest Wakeup Latency
      6. 2.5.6 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL_C1103_C1104 Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 NVM (Flash)
    1. 5.1 NVM Overview
      1. 5.1.1 Key Features
      2. 5.1.2 System Components
      3. 5.1.3 Terminology
    2. 5.2 Flash Memory Bank Organization
      1. 5.2.1 Banks
      2. 5.2.2 Flash Memory Regions
      3. 5.2.3 Addressing
        1. 5.2.3.1 Flash Memory Map
      4. 5.2.4 Memory Organization Examples
    3. 5.3 Flash Controller
      1. 5.3.1 Overview of Flash Controller Commands
      2. 5.3.2 NOOP Command
      3. 5.3.3 PROGRAM Command
        1. 5.3.3.1 Program Bit Masking Behavior
        2. 5.3.3.2 Programming Less Than One Flash Word
        3. 5.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 5.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 5.3.3.5 Executing a PROGRAM Operation
      4. 5.3.4 ERASE Command
        1. 5.3.4.1 Erase Sector Masking Behavior
        2. 5.3.4.2 Executing an ERASE Operation
      5. 5.3.5 READVERIFY Command
        1. 5.3.5.1 Executing a READVERIFY Operation
      6. 5.3.6 BLANKVERIFY Command
        1. 5.3.6.1 Executing a BLANKVERIFY Operation
      7. 5.3.7 Command Diagnostics
        1. 5.3.7.1 Command Status
        2. 5.3.7.2 Address Translation
        3. 5.3.7.3 Pulse Counts
      8. 5.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 5.3.9 FLASHCTL Events
        1. 5.3.9.1 CPU Interrupt Event Publisher
    4. 5.4 Write Protection
      1. 5.4.1 Write Protection Resolution
      2. 5.4.2 Static Write Protection
      3. 5.4.3 Dynamic Write Protection
        1. 5.4.3.1 Configuring Protection for the MAIN Region
        2. 5.4.3.2 Configuring Protection for the NONMAIN Region
    5. 5.5 Read Interface
      1. 5.5.1 Bank Address Swapping
    6. 5.6 FLASHCTL Registers
  8. 6 Events
    1. 6.1 Events Overview
      1. 6.1.1 Event Publisher
      2. 6.1.2 Event Subscriber
      3. 6.1.3 Event Fabric Routing
        1. 6.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 6.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 6.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 6.1.4 Event Routing Map
      5. 6.1.5 Event Propagation Latency
    2. 6.2 Events Operation
      1. 6.2.1 CPU Interrupt
      2. 6.2.2 DMA Trigger
      3. 6.2.3 Peripheral to Peripheral Event
      4. 6.2.4 Extended Module Description Register
      5. 6.2.5 Using Event Registers
        1. 6.2.5.1 Event Registers
        2. 6.2.5.2 Configuring Events
        3. 6.2.5.3 Responding to CPU Interrupts in Application Software
        4. 6.2.5.4 Hardware Event Handling
  9. 7 IOMUX
    1. 7.1 IOMUX Overview
      1. 7.1.1 IO Types and Analog Sharing
    2. 7.2 IOMUX Operation
      1. 7.2.1 Peripheral Function (PF) Assignment
      2. 7.2.2 Logic High to Hi-Z Conversion
      3. 7.2.3 Logic Inversion
      4. 7.2.4 SHUTDOWN Mode Wakeup Logic
      5. 7.2.5 Pullup/Pulldown Resistors
      6. 7.2.6 Drive Strength Control
      7. 7.2.7 Hysteresis and Logic Level Control
    3. 7.3 IOMUX (PINCMx) Register Format
    4. 7.4 IOMUX Registers
  10. 8 GPIO
    1. 8.1 GPIO Overview
    2. 8.2 GPIO Operation
      1. 8.2.1 GPIO Ports
      2. 8.2.2 GPIO Read/Write Interface
      3. 8.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 8.2.4 GPIO Fast Wake
      5. 8.2.5 GPIO DMA Interface
      6. 8.2.6 Event Publishers and Subscribers
    3. 8.3 GPIO Registers
  11. 9 ADC
    1. 9.1 ADC Overview
    2. 9.2 ADC Operation
      1. 9.2.1  ADC Core
      2. 9.2.2  Voltage Reference Options
      3. 9.2.3  Generic Resolution Modes
      4. 9.2.4  Hardware Averaging
      5. 9.2.5  ADC Clocking
      6. 9.2.6  Common ADC Use Cases
      7. 9.2.7  Power Down Behavior
      8. 9.2.8  Sampling Trigger Sources and Sampling Modes
        1. 9.2.8.1 AUTO Sampling Mode
        2. 9.2.8.2 MANUAL Sampling Mode
      9. 9.2.9  Sampling Period
      10. 9.2.10 Conversion Modes
      11. 9.2.11 Data Format
      12. 9.2.12 Advanced Features
        1. 9.2.12.1 Window Comparator
        2. 9.2.12.2 DMA and FIFO Operation
        3. 9.2.12.3 Analog Peripheral Interconnection
      13. 9.2.13 Status Register
      14. 9.2.14 ADC Events
        1. 9.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 9.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 9.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 9.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 9.3 ADC0 Registers
  12. 10VREF
    1. 10.1 VREF Overview
    2. 10.2 VREF Operation
      1. 10.2.1 Internal Reference Generation
    3. 10.3 VREF Registers
  13. 11UART
    1. 11.1 UART Overview
      1. 11.1.1 Purpose of the Peripheral
      2. 11.1.2 Features
      3. 11.1.3 Functional Block Diagram
    2. 11.2 UART Operation
      1. 11.2.1 Clock Control
      2. 11.2.2 Signal Descriptions
      3. 11.2.3 General Architecture and Protocol
        1. 11.2.3.1  Transmit Receive Logic
        2. 11.2.3.2  Bit Sampling
        3. 11.2.3.3  Majority Voting Feature
        4. 11.2.3.4  Baud Rate Generation
        5. 11.2.3.5  Data Transmission
        6. 11.2.3.6  Error and Status
        7. 11.2.3.7  Local Interconnect Network (LIN) Support
          1. 11.2.3.7.1 LIN Responder Transmission Delay
        8. 11.2.3.8  Flow Control
        9. 11.2.3.9  Idle-Line Multiprocessor
        10. 11.2.3.10 9-Bit UART Mode
        11. 11.2.3.11 RS485 Support
        12. 11.2.3.12 DALI Protocol
        13. 11.2.3.13 Manchester Encoding and Decoding
        14. 11.2.3.14 IrDA Encoding and Decoding
        15. 11.2.3.15 ISO7816 Smart Card Support
        16. 11.2.3.16 Address Detection
        17. 11.2.3.17 FIFO Operation
        18. 11.2.3.18 Loopback Operation
        19. 11.2.3.19 Glitch Suppression
      4. 11.2.4 Low Power Operation
      5. 11.2.5 Reset Considerations
      6. 11.2.6 Initialization
      7. 11.2.7 Interrupt and Events Support
        1. 11.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 11.2.8 Emulation Modes
    3. 11.3 UART0 Registers
  14. 12SPI
    1. 12.1 SPI Overview
      1. 12.1.1 Purpose of the Peripheral
      2. 12.1.2 Features
      3. 12.1.3 Functional Block Diagram
      4. 12.1.4 External Connections and Signal Descriptions
    2. 12.2 SPI Operation
      1. 12.2.1 Clock Control
      2. 12.2.2 General Architecture
        1. 12.2.2.1 Chip Select and Command Handling
          1. 12.2.2.1.1 Chip Select Control
          2. 12.2.2.1.2 Command Data Control
        2. 12.2.2.2 Data Format
        3. 12.2.2.3 Delayed data sampling
        4. 12.2.2.4 Clock Generation
        5. 12.2.2.5 FIFO Operation
        6. 12.2.2.6 Loopback mode
        7. 12.2.2.7 DMA Operation
        8. 12.2.2.8 Repeat Transfer mode
        9. 12.2.2.9 Low Power Mode
      3. 12.2.3 Protocol Descriptions
        1. 12.2.3.1 Motorola SPI Frame Format
        2. 12.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 12.2.4 Reset Considerations
      5. 12.2.5 Initialization
      6. 12.2.6 Interrupt and Events Support
        1. 12.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 12.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 12.2.7 Emulation Modes
    3. 12.3 SPI Registers
  15. 13I2C
    1. 13.1 I2C Overview
      1. 13.1.1 Purpose of the Peripheral
      2. 13.1.2 Features
      3. 13.1.3 Functional Block Diagram
      4. 13.1.4 Environment and External Connections
    2. 13.2 I2C Operation
      1. 13.2.1 Clock Control
        1. 13.2.1.1 Clock Select and I2C Speed
        2. 13.2.1.2 Clock Startup
      2. 13.2.2 Signal Descriptions
      3. 13.2.3 General Architecture
        1. 13.2.3.1  I2C Bus Functional Overview
        2. 13.2.3.2  START and STOP Conditions
        3. 13.2.3.3  Data Format with 7-Bit Address
        4. 13.2.3.4  Acknowledge
        5. 13.2.3.5  Repeated Start
        6. 13.2.3.6  SCL Clock Low Timeout
        7. 13.2.3.7  Clock Stretching
        8. 13.2.3.8  Dual Address
        9. 13.2.3.9  Arbitration
        10. 13.2.3.10 Multiple Controller Mode
        11. 13.2.3.11 Glitch Suppression
        12. 13.2.3.12 FIFO operation
          1. 13.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 13.2.3.13 Loopback mode
        14. 13.2.3.14 Burst Mode
        15. 13.2.3.15 DMA Operation
        16. 13.2.3.16 Low-Power Operation
      4. 13.2.4 Protocol Descriptions
        1. 13.2.4.1 I2C Controller Mode
          1. 13.2.4.1.1 Controller Configuration
          2. 13.2.4.1.2 Controller Mode Operation
          3. 13.2.4.1.3 Read On TX Empty
        2. 13.2.4.2 I2C Target Mode
          1. 13.2.4.2.1 Target Mode Operation
      5. 13.2.5 Reset Considerations
      6. 13.2.6 Initialization
      7. 13.2.7 Interrupt and Events Support
        1. 13.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 13.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 13.2.8 Emulation Modes
    3. 13.3 I2C Registers
  16. 14CRC
    1. 14.1 CRC Overview
      1. 14.1.1 CRC16-CCITT
    2. 14.2 CRC Operation
      1. 14.2.1 CRC Generator Implementation
      2. 14.2.2 Configuration
        1. 14.2.2.1 Bit Order
        2. 14.2.2.2 Byte Swap
        3. 14.2.2.3 Byte Order
        4. 14.2.2.4 CRC C Library Compatibility
    3. 14.3 CRC Registers
  17. 15Timers (TIMx)
    1. 15.1 TIMx Overview
      1. 15.1.1 TIMG Overview
        1. 15.1.1.1 TIMG Features
        2. 15.1.1.2 Functional Block Diagram
      2. 15.1.2 TIMA Overview
        1. 15.1.2.1 TIMA Features
        2. 15.1.2.2 Functional Block Diagram
      3. 15.1.3 TIMx Instance Configuration
    2. 15.2 TIMx Operation
      1. 15.2.1  Timer Counter
        1. 15.2.1.1 Clock Source Select and Prescaler
          1. 15.2.1.1.1 Internal Clock and Prescaler
          2. 15.2.1.1.2 External Signal Trigger
        2. 15.2.1.2 Repeat Counter (TIMA only)
      2. 15.2.2  Counting Mode Control
        1. 15.2.2.1 One-shot and Periodic Modes
        2. 15.2.2.2 Down Counting Mode
        3. 15.2.2.3 Up/Down Counting Mode
        4. 15.2.2.4 Up Counting Mode
        5. 15.2.2.5 Phase Load (TIMA only)
      3. 15.2.3  Capture/Compare Module
        1. 15.2.3.1 Capture Mode
          1. 15.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 15.2.3.1.1.1 CCP Input Edge Synchronization
            2. 15.2.3.1.1.2 CCP Input Pulse Conditions
            3. 15.2.3.1.1.3 Counter Control Operation
            4. 15.2.3.1.1.4 CCP Input Filtering
            5. 15.2.3.1.1.5 Input Selection
          2. 15.2.3.1.2 Use Cases
            1. 15.2.3.1.2.1 Edge Time Capture
            2. 15.2.3.1.2.2 Period Capture
            3. 15.2.3.1.2.3 Pulse Width Capture
            4. 15.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 15.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 15.2.3.1.3.1 QEI With 2-Signal
            2. 15.2.3.1.3.2 QEI With Index Input
            3. 15.2.3.1.3.3 QEI Error Detection
          4. 15.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 15.2.3.2 Compare Mode
          1. 15.2.3.2.1 Edge Count
      4. 15.2.4  Shadow Load and Shadow Compare
        1. 15.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 15.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 15.2.5  Output Generator
        1. 15.2.5.1 Configuration
        2. 15.2.5.2 Use Cases
          1. 15.2.5.2.1 Edge-Aligned PWM
          2. 15.2.5.2.2 Center-Aligned PWM
          3. 15.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 15.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 15.2.5.3 Forced Output
      6. 15.2.6  Fault Handler (TIMA only)
        1. 15.2.6.1 Fault Input Conditioning
        2. 15.2.6.2 Fault Input Sources
        3. 15.2.6.3 Counter Behavior With Fault Conditions
        4. 15.2.6.4 Output Behavior With Fault Conditions
      7. 15.2.7  Synchronization With Cross Trigger
        1. 15.2.7.1 Main Timer Cross Trigger Configuration
        2. 15.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 15.2.8  Low Power Operation
      9. 15.2.9  Interrupt and Event Support
        1. 15.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 15.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 15.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 15.2.10 Debug Handler (TIMA Only)
    3. 15.3 TIMx Registers
  18. 16WWDT
    1. 16.1 WWDT Overview
      1. 16.1.1 Watchdog Mode
      2. 16.1.2 Interval Timer Mode
    2. 16.2 WWDT Operation
      1. 16.2.1 Mode Selection
      2. 16.2.2 Clock Configuration
      3. 16.2.3 Low-Power Mode Behavior
      4. 16.2.4 Debug Behavior
      5. 16.2.5 WWDT Events
        1. 16.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 16.3 WWDT Registers
  19. 17Debug
    1. 17.1 Overview
      1. 17.1.1 Debug Interconnect
      2. 17.1.2 Physical Interface
      3. 17.1.3 Debug Access Ports
    2. 17.2 Debug Features
      1. 17.2.1 Processor Debug
        1. 17.2.1.1 Breakpoint Unit (BPU)
        2. 17.2.1.2 Data Watchpoint and Trace Unit (DWT)
      2. 17.2.2 Peripheral Debug
      3. 17.2.3 EnergyTrace Technology
    3. 17.3 Behavior in Low Power Modes
    4. 17.4 Restricting Debug Access
    5. 17.5 Mailbox (DSSM)
      1. 17.5.1 DSSM Events
        1. 17.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 17.5.2 DEBUGSS Registers
  20. 18Revision History

17.5.2 DEBUGSS Registers

Table 17-7 lists the memory-mapped registers for the DEBUGSS registers. All register offset addresses not listed in Table 17-7 should be considered as reserved locations and the register contents should not be modified.

Table 17-7 DEBUGSS Registers
OffsetAcronymRegister NameGroupSection
1020hIIDXInterrupt indexCPU_INTGo
1028hIMASKInterrupt maskCPU_INTGo
1030hRISRaw interrupt statusCPU_INTGo
1038hMISMasked interrupt statusCPU_INTGo
1040hISETInterrupt setCPU_INTGo
1048hICLRInterrupt clearCPU_INTGo
10E0hEVT_MODEEvent ModeGo
10FChDESCModule DescriptionGo
1100hTXDTransmit data registerGo
1104hTXCTLTransmit control registerGo
1108hRXDReceive data registerGo
110ChRXCTLReceive control registerGo
1200hSPECIAL_AUTHSpecial enable authorization registerGo
1210hAPP_AUTHApplication CPU0 authorization registerGo

Complex bit access types are encoded to fit into small table cells. Table 17-8 shows the codes that are used for access types in this section.

Table 17-8 DEBUGSS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
WKW
K		Write
Write protected by a key
Reset or Default Value
-nValue after reset or the default value

17.5.2.1 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 17-2 and described in Table 17-9.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. 0xFF means no event pending. Interrupt 0x0 is the highest priority, 0x1 next highest, and 0xFE is the least priority. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.

On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it displays 0xFF.

Figure 17-2 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 17-9 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
0h = No pending interrupt request
1h = TX interrupt
2h = RX interrupt
3h = Power-up interrupt. A debug session has started.
4h = Power-up interrupt. A debug session has started.

17.5.2.2 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 17-3 and described in Table 17-10.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 17-3 IMASK
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDPWRDWNIFGPWRUPIFGRXIFGTXIFG
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 17-10 IMASK Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3PWRDWNIFGR/W0hMasks PWRDWNIFG in MIS register
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
2PWRUPIFGR/W0hMasks PWRUPIFG in MIS register
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
1RXIFGR/W0hMasks RXIFG in MIS register
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
0TXIFGR/W0hMasks TXIFG in MIS register
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set

17.5.2.3 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 17-4 and described in Table 17-11.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 17-4 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPWRDWNIFGPWRUPIFGRXIFGTXIFG
R-0hR-0hR-0hR-0hR-0h
Table 17-11 RIS Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3PWRDWNIFGR0hRaw interrupt status for PWRDWNIFG
0h = PWRUPIFG did not occur
1h = PWRUPIFG occurred
2PWRUPIFGR0hRaw interrupt status for PWRUPIFG
0h = PWRUPIFG did not occur
1h = PWRUPIFG occurred
1RXIFGR0hRaw interrupt status for RXIFG
0h = RXIFG did not occur
1h = RXIFG occurred
0TXIFGR0hRaw interrupt status for TXIFG
0h = TXIFG did not occur
1h = TXIFG occurred

17.5.2.4 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 17-5 and described in Table 17-12.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 17-5 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPWRDWNIFGPWRUPIFGRXIFGTXIFG
R-0hR-0hR-0hR-0hR-0h
Table 17-12 MIS Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3PWRDWNIFGR0hMasked interrupt status for PWRDWNIFG
0h = PWRUPIFG did not request an interrupt service routine
1h = PWRUPIFG requests an interrupt service routine
2PWRUPIFGR0hMasked interrupt status for PWRUPIFG
0h = PWRUPIFG did not request an interrupt service routine
1h = PWRUPIFG requests an interrupt service routine
1RXIFGR0hMasked interrupt status for RXIFG
0h = RXIFG did not request an interrupt service routine
1h = RXIFG requests an interrupt service routine
0TXIFGR0hMasked interrupt status for TXIFG
0h = TXIFG did not request an interrupt service routine
1h = TXIFG requests an interrupt service routine

17.5.2.5 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 17-6 and described in Table 17-13.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 17-6 ISET
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDPWRDWNIFGPWRUPIFGRXIFGTXIFG
W-0hW-0hW-0hW-0hW-0h
Table 17-13 ISET Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDW0h
3PWRDWNIFGW0hSets PWRDWNIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to PWRUPIFG is set
2PWRUPIFGW0hSets PWRUPIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to PWRUPIFG is set
1RXIFGW0hSets RXIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to RXIFG is set
0TXIFGW0hSets TXIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to TXIFG is set

17.5.2.6 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 17-7 and described in Table 17-14.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 17-7 ICLR
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDPWRDWNIFGPWRUPIFGRXIFGTXIFG
W-0hW-0hW-0hW-0hW-0h
Table 17-14 ICLR Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDW0h
3PWRDWNIFGW0hClears PWRDWNIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to PWRUPIFG is cleared
2PWRUPIFGW0hClears PWRUPIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to PWRUPIFG is cleared
1RXIFGW0hClears RXIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to RXIFG is cleared
0TXIFGW0hClears TXIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to TXIFG is cleared

17.5.2.7 EVT_MODE (Offset = 10E0h) [Reset = 00000001h]

EVT_MODE is shown in Figure 17-8 and described in Table 17-15.

Return to the Summary Table.

Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 17-8 EVT_MODE
3130292827262524
RESERVED
R-
2322212019181716
RESERVED
R-
15141312111098
RESERVED
R-
76543210
RESERVEDINT0_CFG
R-R-1h
Table 17-15 EVT_MODE Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1-0INT0_CFGR1hEvent line mode select for peripheral events
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

17.5.2.8 DESC (Offset = 10FCh) [Reset = 03400000h]

DESC is shown in Figure 17-9 and described in Table 17-16.

Return to the Summary Table.

This register identifies the peripheral and its exact version.

Figure 17-9 DESC
31302928272625242322212019181716
MODULEID
R-340h
1514131211109876543210
FEATUREVERINSTNUMMAJREVMINREV
R-0hR-0hR-0hR-0h
Table 17-16 DESC Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR340hModule identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
15-12FEATUREVERR0hFeature Set for the module *instance*
11-8INSTNUMR0hInstance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
7-4MAJREVR0hMajor rev of the IP
3-0MINREVR0hMinor rev of the IP

17.5.2.9 TXD (Offset = 1100h) [Reset = 00000000h]

TXD is shown in Figure 17-10 and described in Table 17-17.

Return to the Summary Table.

This register is used for data transfers from external debug tools to the DSSM module. The register is written by the debug tool and read by the CPU.

Figure 17-10 TXD
313029282726252423222120191817161514131211109876543210
TX_DATA
R-0h
Table 17-17 TXD Field Descriptions
BitFieldTypeResetDescription
31-0TX_DATAR0hContains data written by an external debug tool to the SEC-AP TXDATA register

17.5.2.10 TXCTL (Offset = 1104h) [Reset = 00000000h]

TXCTL is shown in Figure 17-11 and described in Table 17-18.

Return to the Summary Table.

Transmit control register

Figure 17-11 TXCTL
3130292827262524
TRANSMIT_FLAGS
R-0h
2322212019181716
TRANSMIT_FLAGS
R-0h
15141312111098
TRANSMIT_FLAGS
R-0h
76543210
TRANSMIT_FLAGSTRANSMIT
R-0hR-0h
Table 17-18 TXCTL Field Descriptions
BitFieldTypeResetDescription
31-1TRANSMIT_FLAGSR0hGeneric TX flags that can be set by external debug tool. Functionality is defined by SW.
0TRANSMITR0hIndicates data request in DSSM.TXD, set on write via Debug AP to DSSM.TXD.

A read of the DSSM.TXD register by SW will clear the TX field. The tool can check that TXD is empty by reading this field.

0h = TXD is empty
1h = TXD is full

17.5.2.11 RXD (Offset = 1108h) [Reset = 00000000h]

RXD is shown in Figure 17-12 and described in Table 17-19.

Return to the Summary Table.

Receive data register. This register contains the data written by the CPU.
This data is read by external debug tool.

Figure 17-12 RXD
313029282726252423222120191817161514131211109876543210
RX_DATA
R/W-0h
Table 17-19 RXD Field Descriptions
BitFieldTypeResetDescription
31-0RX_DATAR/W0hContains data written by SM/OW.

17.5.2.12 RXCTL (Offset = 110Ch) [Reset = 00000000h]

RXCTL is shown in Figure 17-13 and described in Table 17-20.

Return to the Summary Table.

Receive control register

Figure 17-13 RXCTL
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RECEIVE_FLAGSRECEIVE
R/W-0hR-0h
Table 17-20 RXCTL Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-1RECEIVE_FLAGSR/W0hGeneric RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW.
0RECEIVER0hIndicates SW write to the DSSM.RXD register.
A read of the DSSM.RXD register by SWD Access Port will clear the RX field.
0h = RXD empty
1h = RXD full

17.5.2.13 SPECIAL_AUTH (Offset = 1200h) [Reset = 00000013h]

SPECIAL_AUTH is shown in Figure 17-14 and described in Table 17-21.

Return to the Summary Table.

This register is used to control ET-AP, DFT-TAP, SWD, CFG-AP and SEC-AP.

Figure 17-14 SPECIAL_AUTH
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPWRAPENAHBAPENCFGAPENETAPENDFTAPENSWDPORTENSECAPEN
R-0hR-0hR-0hR-1hR-0hR-0hR-1hR-1h
Table 17-21 SPECIAL_AUTH Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0h
6PWRAPENR0hAn active high input. When asserted (and SWD access is also permitted), the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted, a DAPBUS firewall will isolate the AP and prevent access.
0h = Disable PWR-AP
1h = Enable PWR-AP
5AHBAPENR0hDisabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation.
0h = Disable AHB-AP
1h = Enable AHB-AP
4CFGAPENR1hAn active high input. When asserted (and SWD access is also permitted), the debug tools can use the Config-AP to read device configuration information. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Config-AP.
0h = Disable CFG-AP
1h = Enable CFG-AP
3ETAPENR0hAn active high input. When asserted (and SWD access is also permitted), the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access.
0h = Disable ET+ -AP
1h = Enable ET+ -AP
2DFTAPENR0hAn active high input. When asserted (and SWD access is also permitted), the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access.
0h = Disable DFT-TAP
1h = Enable DFT-TAP
1SWDPORTENR1hWhen asserted, the SW-DP functions normally.
When deasserted, the SW-DP effectively disables all external debug access.
0h = Disable SWD port
1h = Enable SWD port
0SECAPENR1hAn active high input. When asserted (and SWD access is also permitted), the debug tools can use the Security-AP to communicate with security control logic. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Security-AP.
0h = Disable SEC-AP
1h = Enable SEC-AP

17.5.2.14 APP_AUTH (Offset = 1210h) [Reset = 00000000h]

APP_AUTH is shown in Figure 17-15 and described in Table 17-22.

Return to the Summary Table.

This register is used to control DBGEN, NIDEN, SPIDEN, and SPNIDEN of Application CPU0.
DBGEN, NIDEN are further processed by DSW based on Active and Debug IPF ID.

Figure 17-15 APP_AUTH
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSPNIDENSPIDENNIDENDBGEN
R-0hR-0hR-0hR-0hR-0h
Table 17-22 APP_AUTH Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3SPNIDENR0hSecure noninvasive debug enable.

0h = Invasive debug disabled
1h = Invasive debug enabled
2SPIDENR0hSecure invasive debug enable.

0h = Invasive debug disabled
1h = Invasive debug enabled
1NIDENR0hControls noninvasive debug enable.
0h = Non-invasive debug disabled
1h = Non-invasive debug enabled
0DBGENR0hControls invasive debug enable.

0h = Invasive debug disabled
1h = Invasive debug enabled