SLAU893B October   2023  – July 2024 MSPM0C1103 , MSPM0C1104

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
    5. 1.5 NONMAIN_C1103_C1104 Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 Peripheral Power Enable Control
        1. 2.2.6.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.1.1 SYSOSC FCL in Internal Resistor Mode
          2. 2.3.1.2.2 Disabling SYSOSC
        3. 2.3.1.3 LFCLK_IN (Digital Clock)
        4. 2.3.1.4 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1 MCLK (Main Clock) Tree
        2. 2.3.2.2 CPUCLK (Processor Clock)
        3. 2.3.2.3 ULPCLK (Low-Power Clock)
        4. 2.3.2.4 MFCLK (Middle Frequency Clock)
        5. 2.3.2.5 LFCLK (Low-Frequency Clock)
        6. 2.3.2.6 ADCCLK (ADC Sample Period Clock)
        7. 2.3.2.7 External Clock Output (CLK_OUT)
        8. 2.3.2.8 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 MCLK Monitor
        2. 2.3.4.2 Startup Monitors
          1. 2.3.4.2.1 LFOSC Startup Monitor
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Shutdown Mode Handling
      7. 2.4.7  Configuration Lockout
      8. 2.4.8  System Status
      9. 2.4.9  Error Handling
      10. 2.4.10 SYSCTL Events
        1. 2.4.10.1 CPU Interrupt Event (CPU_INT)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Optimizing for Lowest Wakeup Latency
      6. 2.5.6 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL_C1103_C1104 Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 NVM (Flash)
    1. 5.1 NVM Overview
      1. 5.1.1 Key Features
      2. 5.1.2 System Components
      3. 5.1.3 Terminology
    2. 5.2 Flash Memory Bank Organization
      1. 5.2.1 Banks
      2. 5.2.2 Flash Memory Regions
      3. 5.2.3 Addressing
        1. 5.2.3.1 Flash Memory Map
      4. 5.2.4 Memory Organization Examples
    3. 5.3 Flash Controller
      1. 5.3.1 Overview of Flash Controller Commands
      2. 5.3.2 NOOP Command
      3. 5.3.3 PROGRAM Command
        1. 5.3.3.1 Program Bit Masking Behavior
        2. 5.3.3.2 Programming Less Than One Flash Word
        3. 5.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 5.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 5.3.3.5 Executing a PROGRAM Operation
      4. 5.3.4 ERASE Command
        1. 5.3.4.1 Erase Sector Masking Behavior
        2. 5.3.4.2 Executing an ERASE Operation
      5. 5.3.5 READVERIFY Command
        1. 5.3.5.1 Executing a READVERIFY Operation
      6. 5.3.6 BLANKVERIFY Command
        1. 5.3.6.1 Executing a BLANKVERIFY Operation
      7. 5.3.7 Command Diagnostics
        1. 5.3.7.1 Command Status
        2. 5.3.7.2 Address Translation
        3. 5.3.7.3 Pulse Counts
      8. 5.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 5.3.9 FLASHCTL Events
        1. 5.3.9.1 CPU Interrupt Event Publisher
    4. 5.4 Write Protection
      1. 5.4.1 Write Protection Resolution
      2. 5.4.2 Static Write Protection
      3. 5.4.3 Dynamic Write Protection
        1. 5.4.3.1 Configuring Protection for the MAIN Region
        2. 5.4.3.2 Configuring Protection for the NONMAIN Region
    5. 5.5 Read Interface
      1. 5.5.1 Bank Address Swapping
    6. 5.6 FLASHCTL Registers
  8. 6 Events
    1. 6.1 Events Overview
      1. 6.1.1 Event Publisher
      2. 6.1.2 Event Subscriber
      3. 6.1.3 Event Fabric Routing
        1. 6.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 6.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 6.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 6.1.4 Event Routing Map
      5. 6.1.5 Event Propagation Latency
    2. 6.2 Events Operation
      1. 6.2.1 CPU Interrupt
      2. 6.2.2 DMA Trigger
      3. 6.2.3 Peripheral to Peripheral Event
      4. 6.2.4 Extended Module Description Register
      5. 6.2.5 Using Event Registers
        1. 6.2.5.1 Event Registers
        2. 6.2.5.2 Configuring Events
        3. 6.2.5.3 Responding to CPU Interrupts in Application Software
        4. 6.2.5.4 Hardware Event Handling
  9. 7 IOMUX
    1. 7.1 IOMUX Overview
      1. 7.1.1 IO Types and Analog Sharing
    2. 7.2 IOMUX Operation
      1. 7.2.1 Peripheral Function (PF) Assignment
      2. 7.2.2 Logic High to Hi-Z Conversion
      3. 7.2.3 Logic Inversion
      4. 7.2.4 SHUTDOWN Mode Wakeup Logic
      5. 7.2.5 Pullup/Pulldown Resistors
      6. 7.2.6 Drive Strength Control
      7. 7.2.7 Hysteresis and Logic Level Control
    3. 7.3 IOMUX (PINCMx) Register Format
    4. 7.4 IOMUX Registers
  10. 8 GPIO
    1. 8.1 GPIO Overview
    2. 8.2 GPIO Operation
      1. 8.2.1 GPIO Ports
      2. 8.2.2 GPIO Read/Write Interface
      3. 8.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 8.2.4 GPIO Fast Wake
      5. 8.2.5 GPIO DMA Interface
      6. 8.2.6 Event Publishers and Subscribers
    3. 8.3 GPIO Registers
  11. 9 ADC
    1. 9.1 ADC Overview
    2. 9.2 ADC Operation
      1. 9.2.1  ADC Core
      2. 9.2.2  Voltage Reference Options
      3. 9.2.3  Generic Resolution Modes
      4. 9.2.4  Hardware Averaging
      5. 9.2.5  ADC Clocking
      6. 9.2.6  Common ADC Use Cases
      7. 9.2.7  Power Down Behavior
      8. 9.2.8  Sampling Trigger Sources and Sampling Modes
        1. 9.2.8.1 AUTO Sampling Mode
        2. 9.2.8.2 MANUAL Sampling Mode
      9. 9.2.9  Sampling Period
      10. 9.2.10 Conversion Modes
      11. 9.2.11 Data Format
      12. 9.2.12 Advanced Features
        1. 9.2.12.1 Window Comparator
        2. 9.2.12.2 DMA and FIFO Operation
        3. 9.2.12.3 Analog Peripheral Interconnection
      13. 9.2.13 Status Register
      14. 9.2.14 ADC Events
        1. 9.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 9.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 9.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 9.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 9.3 ADC0 Registers
  12. 10VREF
    1. 10.1 VREF Overview
    2. 10.2 VREF Operation
      1. 10.2.1 Internal Reference Generation
    3. 10.3 VREF Registers
  13. 11UART
    1. 11.1 UART Overview
      1. 11.1.1 Purpose of the Peripheral
      2. 11.1.2 Features
      3. 11.1.3 Functional Block Diagram
    2. 11.2 UART Operation
      1. 11.2.1 Clock Control
      2. 11.2.2 Signal Descriptions
      3. 11.2.3 General Architecture and Protocol
        1. 11.2.3.1  Transmit Receive Logic
        2. 11.2.3.2  Bit Sampling
        3. 11.2.3.3  Majority Voting Feature
        4. 11.2.3.4  Baud Rate Generation
        5. 11.2.3.5  Data Transmission
        6. 11.2.3.6  Error and Status
        7. 11.2.3.7  Local Interconnect Network (LIN) Support
          1. 11.2.3.7.1 LIN Responder Transmission Delay
        8. 11.2.3.8  Flow Control
        9. 11.2.3.9  Idle-Line Multiprocessor
        10. 11.2.3.10 9-Bit UART Mode
        11. 11.2.3.11 RS485 Support
        12. 11.2.3.12 DALI Protocol
        13. 11.2.3.13 Manchester Encoding and Decoding
        14. 11.2.3.14 IrDA Encoding and Decoding
        15. 11.2.3.15 ISO7816 Smart Card Support
        16. 11.2.3.16 Address Detection
        17. 11.2.3.17 FIFO Operation
        18. 11.2.3.18 Loopback Operation
        19. 11.2.3.19 Glitch Suppression
      4. 11.2.4 Low Power Operation
      5. 11.2.5 Reset Considerations
      6. 11.2.6 Initialization
      7. 11.2.7 Interrupt and Events Support
        1. 11.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 11.2.8 Emulation Modes
    3. 11.3 UART0 Registers
  14. 12SPI
    1. 12.1 SPI Overview
      1. 12.1.1 Purpose of the Peripheral
      2. 12.1.2 Features
      3. 12.1.3 Functional Block Diagram
      4. 12.1.4 External Connections and Signal Descriptions
    2. 12.2 SPI Operation
      1. 12.2.1 Clock Control
      2. 12.2.2 General Architecture
        1. 12.2.2.1 Chip Select and Command Handling
          1. 12.2.2.1.1 Chip Select Control
          2. 12.2.2.1.2 Command Data Control
        2. 12.2.2.2 Data Format
        3. 12.2.2.3 Delayed data sampling
        4. 12.2.2.4 Clock Generation
        5. 12.2.2.5 FIFO Operation
        6. 12.2.2.6 Loopback mode
        7. 12.2.2.7 DMA Operation
        8. 12.2.2.8 Repeat Transfer mode
        9. 12.2.2.9 Low Power Mode
      3. 12.2.3 Protocol Descriptions
        1. 12.2.3.1 Motorola SPI Frame Format
        2. 12.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 12.2.4 Reset Considerations
      5. 12.2.5 Initialization
      6. 12.2.6 Interrupt and Events Support
        1. 12.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 12.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 12.2.7 Emulation Modes
    3. 12.3 SPI Registers
  15. 13I2C
    1. 13.1 I2C Overview
      1. 13.1.1 Purpose of the Peripheral
      2. 13.1.2 Features
      3. 13.1.3 Functional Block Diagram
      4. 13.1.4 Environment and External Connections
    2. 13.2 I2C Operation
      1. 13.2.1 Clock Control
        1. 13.2.1.1 Clock Select and I2C Speed
        2. 13.2.1.2 Clock Startup
      2. 13.2.2 Signal Descriptions
      3. 13.2.3 General Architecture
        1. 13.2.3.1  I2C Bus Functional Overview
        2. 13.2.3.2  START and STOP Conditions
        3. 13.2.3.3  Data Format with 7-Bit Address
        4. 13.2.3.4  Acknowledge
        5. 13.2.3.5  Repeated Start
        6. 13.2.3.6  SCL Clock Low Timeout
        7. 13.2.3.7  Clock Stretching
        8. 13.2.3.8  Dual Address
        9. 13.2.3.9  Arbitration
        10. 13.2.3.10 Multiple Controller Mode
        11. 13.2.3.11 Glitch Suppression
        12. 13.2.3.12 FIFO operation
          1. 13.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 13.2.3.13 Loopback mode
        14. 13.2.3.14 Burst Mode
        15. 13.2.3.15 DMA Operation
        16. 13.2.3.16 Low-Power Operation
      4. 13.2.4 Protocol Descriptions
        1. 13.2.4.1 I2C Controller Mode
          1. 13.2.4.1.1 Controller Configuration
          2. 13.2.4.1.2 Controller Mode Operation
          3. 13.2.4.1.3 Read On TX Empty
        2. 13.2.4.2 I2C Target Mode
          1. 13.2.4.2.1 Target Mode Operation
      5. 13.2.5 Reset Considerations
      6. 13.2.6 Initialization
      7. 13.2.7 Interrupt and Events Support
        1. 13.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 13.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 13.2.8 Emulation Modes
    3. 13.3 I2C Registers
  16. 14CRC
    1. 14.1 CRC Overview
      1. 14.1.1 CRC16-CCITT
    2. 14.2 CRC Operation
      1. 14.2.1 CRC Generator Implementation
      2. 14.2.2 Configuration
        1. 14.2.2.1 Bit Order
        2. 14.2.2.2 Byte Swap
        3. 14.2.2.3 Byte Order
        4. 14.2.2.4 CRC C Library Compatibility
    3. 14.3 CRC Registers
  17. 15Timers (TIMx)
    1. 15.1 TIMx Overview
      1. 15.1.1 TIMG Overview
        1. 15.1.1.1 TIMG Features
        2. 15.1.1.2 Functional Block Diagram
      2. 15.1.2 TIMA Overview
        1. 15.1.2.1 TIMA Features
        2. 15.1.2.2 Functional Block Diagram
      3. 15.1.3 TIMx Instance Configuration
    2. 15.2 TIMx Operation
      1. 15.2.1  Timer Counter
        1. 15.2.1.1 Clock Source Select and Prescaler
          1. 15.2.1.1.1 Internal Clock and Prescaler
          2. 15.2.1.1.2 External Signal Trigger
        2. 15.2.1.2 Repeat Counter (TIMA only)
      2. 15.2.2  Counting Mode Control
        1. 15.2.2.1 One-shot and Periodic Modes
        2. 15.2.2.2 Down Counting Mode
        3. 15.2.2.3 Up/Down Counting Mode
        4. 15.2.2.4 Up Counting Mode
        5. 15.2.2.5 Phase Load (TIMA only)
      3. 15.2.3  Capture/Compare Module
        1. 15.2.3.1 Capture Mode
          1. 15.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 15.2.3.1.1.1 CCP Input Edge Synchronization
            2. 15.2.3.1.1.2 CCP Input Pulse Conditions
            3. 15.2.3.1.1.3 Counter Control Operation
            4. 15.2.3.1.1.4 CCP Input Filtering
            5. 15.2.3.1.1.5 Input Selection
          2. 15.2.3.1.2 Use Cases
            1. 15.2.3.1.2.1 Edge Time Capture
            2. 15.2.3.1.2.2 Period Capture
            3. 15.2.3.1.2.3 Pulse Width Capture
            4. 15.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 15.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 15.2.3.1.3.1 QEI With 2-Signal
            2. 15.2.3.1.3.2 QEI With Index Input
            3. 15.2.3.1.3.3 QEI Error Detection
          4. 15.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 15.2.3.2 Compare Mode
          1. 15.2.3.2.1 Edge Count
      4. 15.2.4  Shadow Load and Shadow Compare
        1. 15.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 15.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 15.2.5  Output Generator
        1. 15.2.5.1 Configuration
        2. 15.2.5.2 Use Cases
          1. 15.2.5.2.1 Edge-Aligned PWM
          2. 15.2.5.2.2 Center-Aligned PWM
          3. 15.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 15.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 15.2.5.3 Forced Output
      6. 15.2.6  Fault Handler (TIMA only)
        1. 15.2.6.1 Fault Input Conditioning
        2. 15.2.6.2 Fault Input Sources
        3. 15.2.6.3 Counter Behavior With Fault Conditions
        4. 15.2.6.4 Output Behavior With Fault Conditions
      7. 15.2.7  Synchronization With Cross Trigger
        1. 15.2.7.1 Main Timer Cross Trigger Configuration
        2. 15.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 15.2.8  Low Power Operation
      9. 15.2.9  Interrupt and Event Support
        1. 15.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 15.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 15.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 15.2.10 Debug Handler (TIMA Only)
    3. 15.3 TIMx Registers
  18. 16WWDT
    1. 16.1 WWDT Overview
      1. 16.1.1 Watchdog Mode
      2. 16.1.2 Interval Timer Mode
    2. 16.2 WWDT Operation
      1. 16.2.1 Mode Selection
      2. 16.2.2 Clock Configuration
      3. 16.2.3 Low-Power Mode Behavior
      4. 16.2.4 Debug Behavior
      5. 16.2.5 WWDT Events
        1. 16.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 16.3 WWDT Registers
  19. 17Debug
    1. 17.1 Overview
      1. 17.1.1 Debug Interconnect
      2. 17.1.2 Physical Interface
      3. 17.1.3 Debug Access Ports
    2. 17.2 Debug Features
      1. 17.2.1 Processor Debug
        1. 17.2.1.1 Breakpoint Unit (BPU)
        2. 17.2.1.2 Data Watchpoint and Trace Unit (DWT)
      2. 17.2.2 Peripheral Debug
      3. 17.2.3 EnergyTrace Technology
    3. 17.3 Behavior in Low Power Modes
    4. 17.4 Restricting Debug Access
    5. 17.5 Mailbox (DSSM)
      1. 17.5.1 DSSM Events
        1. 17.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 17.5.2 DEBUGSS Registers
  20. 18Revision History

5.6 FLASHCTL Registers

Table 5-11 lists the memory-mapped registers for the FLASHCTL registers. All register offset addresses not listed in Table 5-11 should be considered as reserved locations and the register contents should not be modified.

Table 5-11 FLASHCTL Registers
OffsetAcronymRegister NameGroupSection
1020hIIDXInterrupt Index RegisterGo
1028hIMASKInterrupt Mask RegisterGo
1030hRISRaw Interrupt Status RegisterGo
1038hMISMasked Interrupt Status RegisterGo
1040hISETInterrupt Set RegisterGo
1048hICLRInterrupt Clear RegisterGo
1100hCMDEXECCommand Execute RegisterGo
1104hCMDTYPECommand Type RegisterGo
1108hCMDCTLCommand Control RegisterGo
1120hCMDADDRCommand Address RegisterGo
1124hCMDBYTENCommand Program Byte Enable RegisterGo
112ChCMDDATAINDEXCommand Data Index RegisterGo
1130hCMDDATA0Command Data Register 0Go
1134hCMDDATA1Command Data Register 1Go
1138hCMDDATA2Command Data Register 2Go
113ChCMDDATA3Command Data Register Bits 127:96Go
1140hCMDDATA4Command Data Register 4Go
1144hCMDDATA5Command Data Register 5Go
1148hCMDDATA6Command Data Register 6Go
114ChCMDDATA7Command Data Register 7Go
1150hCMDDATA8Command Data Register 8Go
1154hCMDDATA9Command Data Register 9Go
1158hCMDDATA10Command Data Register 10Go
115ChCMDDATA11Command Data Register 11Go
1160hCMDDATA12Command Data Register 12Go
1164hCMDDATA13Command Data Register 13Go
1168hCMDDATA14Command Data Register 14Go
116ChCMDDATA15Command Data Register 15Go
1170hCMDDATA16Command Data Register 16Go
1174hCMDDATA17Command Data Register 17Go
1178hCMDDATA18Command Data Register 18Go
117ChCMDDATA19Command Data Register 19Go
1180hCMDDATA20Command Data Register 20Go
1184hCMDDATA21Command Data Register 21Go
1188hCMDDATA22Command Data Register 22Go
118ChCMDDATA23Command Data Register 23Go
1190hCMDDATA24Command Data Register 24Go
1194hCMDDATA25Command Data Register 25Go
1198hCMDDATA26Command Data Register 26Go
119ChCMDDATA27Command Data Register 27Go
11A0hCMDDATA28Command Data Register 28Go
11A4hCMDDATA29Command Data Register 29Go
11A8hCMDDATA30Command Data Register 30Go
11AChCMDDATA31Command Data Register 31Go
11B0hCMDDATAECC0Command Data Register ECC 0Go
11B4hCMDDATAECC1Command Data Register ECC 1Go
11B8hCMDDATAECC2Command Data Register ECC 2Go
11BChCMDDATAECC3Command Data Register ECC 3Go
11C0hCMDDATAECC4Command Data Register ECC 4Go
11C4hCMDDATAECC5Command Data Register ECC 5Go
11C8hCMDDATAECC6Command Data Register ECC 6Go
11CChCMDDATAECC7Command Data Register ECC 7Go
11D0hCMDWEPROTACommand Write Erase Protect A RegisterGo
11D4hCMDWEPROTBCommand Write Erase Protect B RegisterGo
11D8hCMDWEPROTCCommand Write Erase Protect C RegisterGo
1210hCMDWEPROTNMCommand Write Erase Protect Non-Main RegisterGo
13B4hCFGPCNTPulse Counter Configuration RegisterGo
13D0hSTATCMDCommand Status RegisterGo
13D4hSTATADDRAddress Status RegisterGo
13D8hSTATPCNTPulse Count Status RegisterGo

Complex bit access types are encoded to fit into small table cells. Table 5-12 shows the codes that are used for access types in this section.

Table 5-12 FLASHCTL Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

5.6.1 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 5-4 and described in Table 5-13.

Return to the Summary Table.

The interrupt index (IIDX) register provides the index of the highest priority pending and enabled interrupt.

Figure 5-4 IIDX
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSTAT
R-0hR-0h
Table 5-13 IIDX Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0STATR0hIndex corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast, deterministic handling in the interrupt service routine. A read of the IIDX register will clear the corresponding interrupt status in the RIS and MIS registers.
0h (R/W) = No Interrupt Pending
1h (R/W) = DONE Interrupt Pending

5.6.2 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 5-5 and described in Table 5-14.

Return to the Summary Table.

The interrupt mask (IMASK) register holds the current interrupt mask settings.

Figure 5-5 IMASK
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDDONE
R/W-0hR/W-0h
Table 5-14 IMASK Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0hReserved
0DONER/W0hEnable or disable the DONE interrupt.
0h (R/W) = Interrupt is masked out
1h (R/W) = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set

5.6.3 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 5-6 and described in Table 5-15.

Return to the Summary Table.

The raw interrupt status (RIS) register holds the current raw interrupt status.

Figure 5-6 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDONE
R-0hR-0h
Table 5-15 RIS Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DONER0hRaw status of the DONE interrupt.
0h (R/W) = Interrupt did not occur
1h (R/W) = Interrupt occurred

5.6.4 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 5-7 and described in Table 5-16.

Return to the Summary Table.

The masked interrupt status (MIS) register holds the current masked interrupt status.

Figure 5-7 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDONE
R-0hR-0h
Table 5-16 MIS Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DONER0hMasked status of the DONE interrupt.
0h (R/W) = Masked interrupt did not occur
1h (R/W) = Masked interrupt occurred

5.6.5 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 5-8 and described in Table 5-17.

Return to the Summary Table.

The interrupt set (ISET) register may be used to set an interrupt to pending from software.

Figure 5-8 ISET
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDDONE
W-0hW-0h
Table 5-17 ISET Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDW0hReserved
0DONEW0hSet the DONE interrupt.
0h (R/W) = Writing a 0 has no effect
1h (R/W) = Set RIS bit

5.6.6 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 5-9 and described in Table 5-18.

Return to the Summary Table.

The interrupt clear (ICLR) register may be used to clear a pending interrupt.

Figure 5-9 ICLR
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDDONE
W-0hW-0h
Table 5-18 ICLR Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDW0hReserved
0DONEW0hClear the DONE interrupt.
0h (R/W) = Writing a 0 has no effect
1h (R/W) = Clear RIS bit

5.6.7 CMDEXEC (Offset = 1100h) [Reset = 00000000h]

CMDEXEC is shown in Figure 5-10 and described in Table 5-19.

Return to the Summary Table.

Command Execute Register
Initiates execution of the command specified in the CMDTYPE register. This register is blocked for writes after being written to 1 and prior to STATCMD.DONE being set by hardware. Hardware clears this register after the processing of the command has completed.

Figure 5-10 CMDEXEC
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDVAL
R/W-0hR/W-0h
Table 5-19 CMDEXEC Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0hReserved
0VALR/W0hCommand Execute value Initiates execution of the command specified in the CMDTYPE register.
0h (R/W) = Command will not execute or is not executing in hardware
1h (R/W) = Command will execute or is executing in hardware

5.6.8 CMDTYPE (Offset = 1104h) [Reset = 00000000h]

CMDTYPE is shown in Figure 5-11 and described in Table 5-20.

Return to the Summary Table.

Command Type Register
Specifies the type of command to be executed by hardware. This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by the hardware to indicate that command execution has completed.

Figure 5-11 CMDTYPE
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDSIZERESERVEDCOMMAND
R/W-0hR/W-0hR/W-0hR/W-0h
Table 5-20 CMDTYPE Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR/W0hReserved
6-4SIZER/W0hCommand size
0h (R/W) = Operate on 1 flash word
1h (R/W) = Operate on 2 flash words
2h (R/W) = Operate on 4 flash words
3h (R/W) = Operate on 8 flash words
4h (R/W) = Operate on a flash sector
5h (R/W) = Operate on an entire flash bank
3RESERVEDR/W0hReserved
2-0COMMANDR/W0hCommand type
0h (R/W) = No Operation
1h (R/W) = Program
2h (R/W) = Erase
3h (R/W) = Read Verify - Perform a standalone read verify operation.
6h (R/W) = Blank Verify - Check whether a flash word is in the erased state. This command may only be used with CMDTYPE.SIZE = ONEWORD

5.6.9 CMDCTL (Offset = 1108h) [Reset = 00000000h]

CMDCTL is shown in Figure 5-12 and described in Table 5-21.

Return to the Summary Table.

Command Control Register This register configures specific capabilities of the state machine for related to the execution of a command. This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by the hardware to indicate that command execution has completed.

Figure 5-12 CMDCTL
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVEDRESERVEDSSERASEDISRESERVEDECCGENOVRADDRXLATEOVR
R/W-0hR/W-R/W-0hR/W-R/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDREGIONSELRESERVED
R/W-R/W-0hR/W-0hR/W-
76543210
RESERVEDBANKSELRESERVED
R/W-R/W-0hR/W-
Table 5-21 CMDCTL Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR/W0hReserved
21RESERVEDR/W0h
20SSERASEDISR/W0hDisable Stair-Step Erase. If set, the default VHV trim voltage setting will be used for all erase pulses. By default, this bit is reset, meaning that the VHV voltage will be stepped during successive erase pulses. The step count, step voltage, begin and end voltages are all hard-wired.
0h (R/W) = Enable
1h (R/W) = Disable
19-18RESERVEDR/W0h
17ECCGENOVRR/W0hOverride hardware generation of ECC data for program. Use data written to CMDDATAECC*.
0h (R/W) = Do not override
1h (R/W) = Override
16ADDRXLATEOVRR/W0hOverride hardware address translation of address in CMDADDR from a system address to the corresponding bank address and bank ID. When set, CMDADDR will be used directly as the bank address, CMDCTL.REGIONSEL will be used directly as the region ID, and CMDCTL.BANKSEL will be used directly as the bank ID (if the device contains multiple banks).
0h (R/W) = Do not override
1h (R/W) = Override
15-14RESERVEDR/W0h
13RESERVEDR/W0hReserved
12-9REGIONSELR/W0hBank Region A specific region ID can be written to this field to indicate to which region an operation should be applied if CMDCTL.ADDRXLATEOVR is set.
1h (R/W) = Main Region
2h (R/W) = Non-Main Region
8-5RESERVEDR/W0h
4BANKSELR/W0hBank Select A specific Bank ID can be written to this field to indicate to which bank an operation should be applied if CMDCTL.ADDRXLATEOVR is set.
1h (R/W) = Bank 0
2h (R/W) = Bank 1
4h (R/W) = Bank 2
8h (R/W) = Bank 3
10h (R/W) = Bank 4
3-0RESERVEDR/W0h

5.6.10 CMDADDR (Offset = 1120h) [Reset = 00000000h]

CMDADDR is shown in Figure 5-13 and described in Table 5-22.

Return to the Summary Table.

Command Address Register:
This register forms the target address of a command. The use cases are as follows:
1) For single-word program, this address indicates the flash bank word to be programmed.
2) For multi-word program, this address indicates the first flash bank address for the program. The address will be incremented for further words.
3) For sector erase, this address indicates the sector to be erased.
4) For bank erase, the address indicates the bank to be erased.
5) For read verify, the address indications follow program/erase listed above.
Note the address written to this register will be submitted for translation to the flash address translation interface, and the translated address will be used to access the bank. However, if the CMDCTL.ADDRXLATEOVR bit is set, then the address written to this register will be used directly as the bank address.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.

Figure 5-13 CMDADDR
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 5-22 CMDADDR Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hAddress value
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.11 CMDBYTEN (Offset = 1124h) [Reset = 00000000h]

CMDBYTEN is shown in Figure 5-14 and described in Table 5-23.

Return to the Summary Table.

Command Program Byte Enable Register:
This register forms a per-byte enable for programming data. For data bytes to be programmed, a 1 must be written to the corresponding bit in this register. Normally, all bits are written to 1, allowing program of full flash words. However, leaving some bits 0 allows programming of 8-bit, 16-bit, 32-bit or 64-bit portions of a flash word.
In addition, the read verify command will ignore data bytes read from the flash in its comparison if the corresponding CMDBYTEN bit is 0.
For 64-bit flash word size devices, the CMDBYTEN register uses BIT7-0 to enable each data byte and BIT8 to enable the ECC code byte.
For 128-bit flash word size devices, the CMDBYTEN register uses BIT15-0 to enable each data byte and BIT17-16 to enable each ECC code byte.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is written to all 0 after the completion of all commands.

Figure 5-14 CMDBYTEN
313029282726252423222120191817161514131211109876543210
RESERVEDRESERVEDVAL
R/W-0hR/W-R/W-0h
Table 5-23 CMDBYTEN Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/W0hReserved
17-8RESERVEDR/W0h
7-0VALR/W0hCommand Byte Enable value. A 1-bit per flash word byte value is placed in this register.
0h = Minimum value of [VAL]
0003FFFFh = Maximum value of [VAL]

5.6.12 CMDDATAINDEX (Offset = 112Ch) [Reset = 00000000h]

CMDDATAINDEX is shown in Figure 5-15 and described in Table 5-24.

Return to the Summary Table.

Command Program Data Index Register:
When multiple data registers are available for multi-word program, this register can be written with an index which points to one of the data registers. When a write to CMDDATA* is done, the data will be written to the physical data register indexed by the value in this register.
Up to 8 data registers can be present, so this register can be written with 0x0 to 0x7. If less than 8 data registers are present, successive MSB bits of this register are ignored when indexing the CMDDATA* registers.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.

Figure 5-15 CMDDATAINDEX
313029282726252423222120191817161514131211109876543210
RESERVEDVAL
R/W-0hR/W-0h
Table 5-24 CMDDATAINDEX Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0hReserved
2-0VALR/W0hData register index
0h = Minimum value of [VAL]
7h = Maximum value of [VAL]

5.6.13 CMDDATA0 (Offset = 1130h) [Reset = FFFFFFFFh]

CMDDATA0 is shown in Figure 5-16 and described in Table 5-25.

Return to the Summary Table.

Command Data Register 0
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 0.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-16 CMDDATA0
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-25 CMDDATA0 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.14 CMDDATA1 (Offset = 1134h) [Reset = FFFFFFFFh]

CMDDATA1 is shown in Figure 5-17 and described in Table 5-26.

Return to the Summary Table.

Command Data Register 1
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 0.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-17 CMDDATA1
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-26 CMDDATA1 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.15 CMDDATA2 (Offset = 1138h) [Reset = FFFFFFFFh]

CMDDATA2 is shown in Figure 5-18 and described in Table 5-27.

Return to the Summary Table.

Command Data Register 2
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 1.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-18 CMDDATA2
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-27 CMDDATA2 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.16 CMDDATA3 (Offset = 113Ch) [Reset = FFFFFFFFh]

CMDDATA3 is shown in Figure 5-19 and described in Table 5-28.

Return to the Summary Table.

Command Data Register 3
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 1.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-19 CMDDATA3
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-28 CMDDATA3 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.17 CMDDATA4 (Offset = 1140h) [Reset = FFFFFFFFh]

CMDDATA4 is shown in Figure 5-20 and described in Table 5-29.

Return to the Summary Table.

Command Data Register 4
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 2.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-20 CMDDATA4
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-29 CMDDATA4 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field. T
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.18 CMDDATA5 (Offset = 1144h) [Reset = FFFFFFFFh]

CMDDATA5 is shown in Figure 5-21 and described in Table 5-30.

Return to the Summary Table.

Command Data Register 5
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 2.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-21 CMDDATA5
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-30 CMDDATA5 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.19 CMDDATA6 (Offset = 1148h) [Reset = FFFFFFFFh]

CMDDATA6 is shown in Figure 5-22 and described in Table 5-31.

Return to the Summary Table.

Command Data Register 6
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 3.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-22 CMDDATA6
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-31 CMDDATA6 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.20 CMDDATA7 (Offset = 114Ch) [Reset = FFFFFFFFh]

CMDDATA7 is shown in Figure 5-23 and described in Table 5-32.

Return to the Summary Table.

Command Data Register 7
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 3.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-23 CMDDATA7
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-32 CMDDATA7 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.21 CMDDATA8 (Offset = 1150h) [Reset = FFFFFFFFh]

CMDDATA8 is shown in Figure 5-24 and described in Table 5-33.

Return to the Summary Table.

Command Data Register 8
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-24 CMDDATA8
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-33 CMDDATA8 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.22 CMDDATA9 (Offset = 1154h) [Reset = FFFFFFFFh]

CMDDATA9 is shown in Figure 5-25 and described in Table 5-34.

Return to the Summary Table.

Command Data Register 9
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-25 CMDDATA9
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-34 CMDDATA9 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.23 CMDDATA10 (Offset = 1158h) [Reset = FFFFFFFFh]

CMDDATA10 is shown in Figure 5-26 and described in Table 5-35.

Return to the Summary Table.

Command Data Register 10
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-26 CMDDATA10
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-35 CMDDATA10 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.24 CMDDATA11 (Offset = 115Ch) [Reset = FFFFFFFFh]

CMDDATA11 is shown in Figure 5-27 and described in Table 5-36.

Return to the Summary Table.

Command Data Register 11
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-27 CMDDATA11
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-36 CMDDATA11 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.25 CMDDATA12 (Offset = 1160h) [Reset = FFFFFFFFh]

CMDDATA12 is shown in Figure 5-28 and described in Table 5-37.

Return to the Summary Table.

Command Data Register 12
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-28 CMDDATA12
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-37 CMDDATA12 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.26 CMDDATA13 (Offset = 1164h) [Reset = FFFFFFFFh]

CMDDATA13 is shown in Figure 5-29 and described in Table 5-38.

Return to the Summary Table.

Command Data Register 13
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-29 CMDDATA13
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-38 CMDDATA13 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.27 CMDDATA14 (Offset = 1168h) [Reset = FFFFFFFFh]

CMDDATA14 is shown in Figure 5-30 and described in Table 5-39.

Return to the Summary Table.

Command Data Register 14
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-30 CMDDATA14
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-39 CMDDATA14 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.28 CMDDATA15 (Offset = 116Ch) [Reset = FFFFFFFFh]

CMDDATA15 is shown in Figure 5-31 and described in Table 5-40.

Return to the Summary Table.

Command Data Register 15
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-31 CMDDATA15
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-40 CMDDATA15 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.29 CMDDATA16 (Offset = 1170h) [Reset = FFFFFFFFh]

CMDDATA16 is shown in Figure 5-32 and described in Table 5-41.

Return to the Summary Table.

Command Data Register 16
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-32 CMDDATA16
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-41 CMDDATA16 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.30 CMDDATA17 (Offset = 1174h) [Reset = FFFFFFFFh]

CMDDATA17 is shown in Figure 5-33 and described in Table 5-42.

Return to the Summary Table.

Command Data Register 17
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-33 CMDDATA17
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-42 CMDDATA17 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.31 CMDDATA18 (Offset = 1178h) [Reset = FFFFFFFFh]

CMDDATA18 is shown in Figure 5-34 and described in Table 5-43.

Return to the Summary Table.

Command Data Register 18
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-34 CMDDATA18
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-43 CMDDATA18 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.32 CMDDATA19 (Offset = 117Ch) [Reset = FFFFFFFFh]

CMDDATA19 is shown in Figure 5-35 and described in Table 5-44.

Return to the Summary Table.

Command Data Register 19
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-35 CMDDATA19
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-44 CMDDATA19 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.33 CMDDATA20 (Offset = 1180h) [Reset = FFFFFFFFh]

CMDDATA20 is shown in Figure 5-36 and described in Table 5-45.

Return to the Summary Table.

Command Data Register 20
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-36 CMDDATA20
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-45 CMDDATA20 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.34 CMDDATA21 (Offset = 1184h) [Reset = FFFFFFFFh]

CMDDATA21 is shown in Figure 5-37 and described in Table 5-46.

Return to the Summary Table.

Command Data Register 21
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-37 CMDDATA21
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-46 CMDDATA21 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.35 CMDDATA22 (Offset = 1188h) [Reset = FFFFFFFFh]

CMDDATA22 is shown in Figure 5-38 and described in Table 5-47.

Return to the Summary Table.

Command Data Register 22
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-38 CMDDATA22
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-47 CMDDATA22 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.36 CMDDATA23 (Offset = 118Ch) [Reset = FFFFFFFFh]

CMDDATA23 is shown in Figure 5-39 and described in Table 5-48.

Return to the Summary Table.

Command Data Register 23
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-39 CMDDATA23
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-48 CMDDATA23 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.37 CMDDATA24 (Offset = 1190h) [Reset = FFFFFFFFh]

CMDDATA24 is shown in Figure 5-40 and described in Table 5-49.

Return to the Summary Table.

Command Data Register 24
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-40 CMDDATA24
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-49 CMDDATA24 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.38 CMDDATA25 (Offset = 1194h) [Reset = FFFFFFFFh]

CMDDATA25 is shown in Figure 5-41 and described in Table 5-50.

Return to the Summary Table.

Command Data Register 25
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-41 CMDDATA25
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-50 CMDDATA25 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.39 CMDDATA26 (Offset = 1198h) [Reset = FFFFFFFFh]

CMDDATA26 is shown in Figure 5-42 and described in Table 5-51.

Return to the Summary Table.

Command Data Register 26
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-42 CMDDATA26
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-51 CMDDATA26 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.40 CMDDATA27 (Offset = 119Ch) [Reset = FFFFFFFFh]

CMDDATA27 is shown in Figure 5-43 and described in Table 5-52.

Return to the Summary Table.

Command Data Register 27
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-43 CMDDATA27
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-52 CMDDATA27 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.41 CMDDATA28 (Offset = 11A0h) [Reset = FFFFFFFFh]

CMDDATA28 is shown in Figure 5-44 and described in Table 5-53.

Return to the Summary Table.

Command Data Register 28
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-44 CMDDATA28
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-53 CMDDATA28 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.42 CMDDATA29 (Offset = 11A4h) [Reset = FFFFFFFFh]

CMDDATA29 is shown in Figure 5-45 and described in Table 5-54.

Return to the Summary Table.

Command Data Register 29
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-45 CMDDATA29
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-54 CMDDATA29 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.43 CMDDATA30 (Offset = 11A8h) [Reset = FFFFFFFFh]

CMDDATA30 is shown in Figure 5-46 and described in Table 5-55.

Return to the Summary Table.

Command Data Register 30
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-46 CMDDATA30
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-55 CMDDATA30 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.44 CMDDATA31 (Offset = 11ACh) [Reset = FFFFFFFFh]

CMDDATA31 is shown in Figure 5-47 and described in Table 5-56.

Return to the Summary Table.

Command Data Register 31
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 5-47 CMDDATA31
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-56 CMDDATA31 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.45 CMDDATAECC0 (Offset = 11B0h) [Reset = 0000FFFFh]

CMDDATAECC0 is shown in Figure 5-48 and described in Table 5-57.

Return to the Summary Table.

Command Data Register 0
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 0.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.

Figure 5-48 CMDDATAECC0
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R/W-0hR/W-FFhR/W-FFh
Table 5-57 CMDDATAECC0 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
0h = Minimum value
FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
0h = Minimum value
FFh = Maximum value

5.6.46 CMDDATAECC1 (Offset = 11B4h) [Reset = 0000FFFFh]

CMDDATAECC1 is shown in Figure 5-49 and described in Table 5-58.

Return to the Summary Table.

Command Data Register 1
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 1.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.

Figure 5-49 CMDDATAECC1
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R/W-0hR/W-FFhR/W-FFh
Table 5-58 CMDDATAECC1 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
0h = Minimum value
FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
0h = Minimum value
FFh = Maximum value

5.6.47 CMDDATAECC2 (Offset = 11B8h) [Reset = 0000FFFFh]

CMDDATAECC2 is shown in Figure 5-50 and described in Table 5-59.

Return to the Summary Table.

Command Data Register 2
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 2.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.

Figure 5-50 CMDDATAECC2
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R/W-0hR/W-FFhR/W-FFh
Table 5-59 CMDDATAECC2 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
0h = Minimum value
FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
0h = Minimum value
FFh = Maximum value

5.6.48 CMDDATAECC3 (Offset = 11BCh) [Reset = 0000FFFFh]

CMDDATAECC3 is shown in Figure 5-51 and described in Table 5-60.

Return to the Summary Table.

Command Data Register 3
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 3.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.

Figure 5-51 CMDDATAECC3
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R/W-0hR/W-FFhR/W-FFh
Table 5-60 CMDDATAECC3 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
0h = Minimum value
FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
0h = Minimum value
FFh = Maximum value

5.6.49 CMDDATAECC4 (Offset = 11C0h) [Reset = 0000FFFFh]

CMDDATAECC4 is shown in Figure 5-52 and described in Table 5-61.

Return to the Summary Table.

Command Data Register 4
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 4.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.

Figure 5-52 CMDDATAECC4
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R/W-0hR/W-FFhR/W-FFh
Table 5-61 CMDDATAECC4 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
0h = Minimum value
FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
0h = Minimum value
FFh = Maximum value

5.6.50 CMDDATAECC5 (Offset = 11C4h) [Reset = 0000FFFFh]

CMDDATAECC5 is shown in Figure 5-53 and described in Table 5-62.

Return to the Summary Table.

Command Data Register 5
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 5.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.

Figure 5-53 CMDDATAECC5
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R/W-0hR/W-FFhR/W-FFh
Table 5-62 CMDDATAECC5 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
0h = Minimum value
FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
0h = Minimum value
FFh = Maximum value

5.6.51 CMDDATAECC6 (Offset = 11C8h) [Reset = 0000FFFFh]

CMDDATAECC6 is shown in Figure 5-54 and described in Table 5-63.

Return to the Summary Table.

Command Data Register 6
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 6.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.

Figure 5-54 CMDDATAECC6
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R/W-0hR/W-FFhR/W-FFh
Table 5-63 CMDDATAECC6 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
0h = Minimum value
FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
0h = Minimum value
FFh = Maximum value

5.6.52 CMDDATAECC7 (Offset = 11CCh) [Reset = 0000FFFFh]

CMDDATAECC7 is shown in Figure 5-55 and described in Table 5-64.

Return to the Summary Table.

Command Data Register 7
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 7.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.

Figure 5-55 CMDDATAECC7
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R/W-0hR/W-FFhR/W-FFh
Table 5-64 CMDDATAECC7 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
0h = Minimum value
FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
0h = Minimum value
FFh = Maximum value

5.6.53 CMDWEPROTA (Offset = 11D0h) [Reset = FFFFFFFFh]

CMDWEPROTA is shown in Figure 5-56 and described in Table 5-65.

Return to the Summary Table.

Command WriteErase Protect A Register
This register allows the first 32 sectors of the main region to be protected from program or erase, with 1 bit protecting each sector. If the main region size is smaller than 32 sectors, then this register provides protection for the whole region.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all commands.

Figure 5-56 CMDWEPROTA
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-65 CMDWEPROTA Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhEach bit protects 1 sector. bit [0]: When 1, sector 0 of the flash memory will be protected from program and erase. bit [1]: When 1, sector 1 of the flash memory will be protected from program and erase. : : bit [31]: When 1, sector 31 of the flash memory will be protected from program and erase.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.54 CMDWEPROTB (Offset = 11D4h) [Reset = FFFFFFFFh]

CMDWEPROTB is shown in Figure 5-57 and described in Table 5-66.

Return to the Summary Table.

Command WriteErase Protect B Register
This register allows main region sectors to be protected from program and erase. Each bit corresponds to a group of 8 sectors. There are 3 cases for how these protect bits are applied:
1. Single-bank system:
In the case where only a single flash bank is present, the first 32 sectors are protected via the CMDWEPROTA register. Thus, the protection give by the bits in CMDWEPROTB begin with sector 32.
2. Multi-bank system, Bank 0:
When multiple flash banks are present, the first 32 sectors of bank 0 are protected via the CMDWEPROTA register. Thus, only bits 4 and above of CMDWEPROTB would be applicable to bank 0. The protection of bit 4 and above would begin at sector 32. Bits 3:0 of WEPROTB are ignored for bank 0.
3. Multi-bank system, Banks 1-N:
For banks other than bank 0 in a multi-bank system, CMDWEPROTA has no effect, so the bits in CMDWEPROTB will protect these banks starting from sector 0.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all commands.

Figure 5-57 CMDWEPROTB
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-66 CMDWEPROTB Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhEach bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. A maximum of 256 sectors can be protected with this register.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.55 CMDWEPROTC (Offset = 11D8h) [Reset = FFFFFFFFh]

CMDWEPROTC is shown in Figure 5-58 and described in Table 5-67.

Return to the Summary Table.

Command WriteErase Protect C Register
This register allows main region sectors to be protected from program and erase. Each bit corresponds to a group of 8 sectors.
This register extends the protection bits from the CMDWEPROTB register to cover bank sizes larger than 32*8=256 sectors. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all commands.

Figure 5-58 CMDWEPROTC
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-67 CMDWEPROTC Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhEach bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. Note that the sectors protected with this register start at sector 256 in the flash, where the sectors protected by the CMDWEPROTB register end.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.56 CMDWEPROTNM (Offset = 1210h) [Reset = FFFFFFFFh]

CMDWEPROTNM is shown in Figure 5-59 and described in Table 5-68.

Return to the Summary Table.

Command WriteErase Protect Non-Main Register
This register allows nonmain region sectors to be protected from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all commands.

Figure 5-59 CMDWEPROTNM
313029282726252423222120191817161514131211109876543210
VAL
R/W-FFFFFFFFh
Table 5-68 CMDWEPROTNM Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhEach bit protects 1 sector. bit [0]: When 1, sector 0 of the nonmain region will be protected from program and erase. bit [1]: When 1, sector 1 of the nonmain region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the nonmain will be protected from program and erase.
0h = Minimum value of [VAL]
FFFFFFFFh = Maximum value of [VAL]

5.6.57 CFGPCNT (Offset = 13B4h) [Reset = 00000000h]

CFGPCNT is shown in Figure 5-60 and described in Table 5-69.

Return to the Summary Table.

Pulse Counter Configuration Register
This register allows further configuration of maximum pulse counts for program and erase operations.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.

Figure 5-60 CFGPCNT
3130292827262524
MAXERSPCNTVAL
R/W-0h
2322212019181716
MAXERSPCNTVALRESERVEDMAXERSPCNTOVR
R/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDMAXPCNTVAL
R/W-0hR/W-0h
76543210
MAXPCNTVALRESERVEDMAXPCNTOVR
R/W-0hR/W-0hR/W-0h
Table 5-69 CFGPCNT Field Descriptions
BitFieldTypeResetDescription
31-20MAXERSPCNTVALR/W0hOverride maximum pulse count for erase with this value. If MAXERSPCNTOVR = 0, then this field is ignored. If MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for erase.
0h = Minimum value
FFFh = Maximum value
19-17RESERVEDR/W0hReserved
16MAXERSPCNTOVRR/W0hOverride hard-wired maximum pulse count for erase. If set, then the value in MAXERSPCNTVAL will be used as the max pulse count for erase operations. By default, this bit is 0, and a hard-wired max pulse count is used.
0h = Use hard-wired (default) value for maximum pulse count
1h = Use value from MAXERSPCNTVAL field as maximum erase pulse count
15-12RESERVEDR/W0hReserved
11-4MAXPCNTVALR/W0hOverride maximum pulse counter with this value. If MAXPCNTOVR = 0, then this field is ignored. If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used to override the max pulse count for both program and erase. Full max value will be {4'h0, MAXPCNTVAL} . If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for program only. Full max value will be {4'h0, MAXPCNTVAL}.
0h = Minimum value
FFh = Maximum value
3-1RESERVEDR/W0hReserved
0MAXPCNTOVRR/W0hOverride hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count setting for program. By default, this bit is 0, and a hard-wired max pulse count is used.
0h = Use hard-wired (default) value for maximum pulse count
1h = Use value from MAXPCNTVAL field as maximum pulse count

5.6.58 STATCMD (Offset = 13D0h) [Reset = 00000000h]

STATCMD is shown in Figure 5-61 and described in Table 5-70.

Return to the Summary Table.

Command Status Register This register contains status regarding completion and errors of command execution.

Figure 5-61 STATCMD
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDFAILMISCRESERVEDRESERVED
R-0hR-0hR-0hR-
76543210
FAILMODEFAILILLADDRFAILVERIFYFAILWEPROTRESERVEDCMDINPROGRESSCMDPASSCMDDONE
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 5-70 STATCMD Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0hReserved
12FAILMISCR0hCommand failed due to error other than write/erase protect violation or verify error. This is an extra bit in case a new failure mechanism is added which requires a status bit.
0h = No Fail
1h = Fail
11-9RESERVEDR0hReserved
8RESERVEDR0h
7FAILMODER0hCommand failed because a bank has been set to a mode other than READ. Program and Erase commands cannot be initiated unless all banks are in READ mode.
0h = No Fail
1h = Fail
6FAILILLADDRR0hCommand failed due to the use of an illegal address
0h = No Fail
1h = Fail
5FAILVERIFYR0hCommand failed due to verify error
0h = No Fail
1h = Fail
4FAILWEPROTR0hCommand failed due to Write/Erase Protect Sector Violation
0h = No Fail
1h = Fail
3RESERVEDR0hReserved
2CMDINPROGRESSR0hCommand In Progress
0h = Complete
1h = In Progress
1CMDPASSR0hCommand Pass - valid when CMD_DONE field is 1
0h = Fail
1h = Pass
0CMDDONER0hCommand Done
0h = Not Done
1h = Done

5.6.59 STATADDR (Offset = 13D4h) [Reset = 00010000h]

STATADDR is shown in Figure 5-62 and described in Table 5-71.

Return to the Summary Table.

Current Address Counter Value Read only register giving read access to the state machine current address. A bank id, region id and address are stored in this register and are incremented as necessary during execution of a command.

Figure 5-62 STATADDR
31302928272625242322212019181716
RESERVEDBANKIDREGIONID
R-0hR-0hR-1h
1514131211109876543210
BANKADDR
R-0h
Table 5-71 STATADDR Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-21BANKIDR0hCurrent Bank ID A bank indicator is stored in this register which represents the current bank on which the state machine is operating. There is 1 bit per bank.
1h (R/W) = Bank 0
2h (R/W) = Bank 1
4h (R/W) = Bank 2
8h (R/W) = Bank 3
10h (R/W) = Bank 4
20-16REGIONIDR1hCurrent Region ID A region indicator is stored in this register which represents the current flash region on which the state machine is operating.
1h (R/W) = Main Region
2h (R/W) = Non-Main Region
4h (R/W) = Trim Region
8h (R/W) = Engr Region
15-0BANKADDRR0hCurrent Bank Address A bank offset address is stored in this register.
0h = Minimum value
FFFFh = Maximum value

5.6.60 STATPCNT (Offset = 13D8h) [Reset = 00000000h]

STATPCNT is shown in Figure 5-63 and described in Table 5-72.

Return to the Summary Table.

Current Pulse Count Register: Read only register giving read access to the state machine current pulse count value for program/erase operations.

Figure 5-63 STATPCNT
313029282726252423222120191817161514131211109876543210
RESERVEDPULSECNT
R-0hR-0h
Table 5-72 STATPCNT Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0PULSECNTR0hCurrent Pulse Counter Value
0h = Minimum value
FFFh = Maximum value