SLAU893B October 2023 – July 2024 MSPM0C1103 , MSPM0C1104
Table 14-2 lists the memory-mapped registers for the CRC registers. All register offset addresses not listed in Table 14-2 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
800h | PWREN | Power enable | Go | |
804h | RSTCTL | Reset Control | Go | |
814h | STAT | Status Register | Go | |
1004h | CLKSEL | Clock Select | Go | |
10FCh | DESC | Module Description | Go | |
1100h | CRCCTRL | CRC Control Register | Go | |
1104h | CRCSEED | CRC Seed Register | Go | |
1108h | CRCIN | CRC Input Data Register | Go | |
110Ch | CRCOUT | CRC Output Result Register | Go | |
1800h + formula | CRCIN_IDX[y] | CRC Input Data Array Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 14-3 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
H | H | Set or cleared by hardware |
R | R | Read |
Write Type | ||
W | W | Write |
WK | W K | Write Write protected by a key |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
PWREN is shown in Figure 14-1 and described in Table 14-4.
Return to the Summary Table.
Register to control the power state
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R/W-0h | R/WK-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | KEY to allow Power State Change
26h = KEY to allow write access to this register |
23-1 | RESERVED | R/W | 0h | |
0 | ENABLE | R/WK | 0h | Enable the power KEY must be set to 26h to write to this bit. 0h = Disable Power 1h = Enable Power |
RSTCTL is shown in Figure 14-2 and described in Table 14-5.
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Register to control reset assertion and de-assertion
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETSTKYCLR | RESETASSERT | |||||
R-0h | WK-0h | WK-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | Unlock key
B1h = KEY to allow write access to this register |
23-2 | RESERVED | R | 0h | Reserved |
1 | RESETSTKYCLR | WK | 0h | Clear the RESETSTKY bit in the STAT register KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Clear reset sticky bit |
0 | RESETASSERT | WK | 0h | Assert reset to the peripheral KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Assert reset |
STAT is shown in Figure 14-3 and described in Table 14-6.
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peripheral enable and reset status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESETSTKY | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | Reserved |
16 | RESETSTKY | R | 0h | This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 1h = The peripheral was reset since the last bit clear |
15-0 | RESERVED | R | 0h | Reserved |
CLKSEL is shown in Figure 14-4 and described in Table 14-7.
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Clock source selection
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MCLK_SEL | ||||||
R-0h | R-1h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | |
0 | MCLK_SEL | R | 1h | Selects main clock (MCLK) if enabled
0h = Does not select this clock as a source 1h = Select this clock as a source |
DESC is shown in Figure 14-5 and described in Table 14-8.
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This register identifies the peripheral and its exact version.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODULEID | |||||||||||||||
R-2011h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FEATUREVER | INSTNUM | MAJREV | MINREV | ||||||||||||
R-7h | R-0h | R-1h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODULEID | R | 2011h | Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0h = Smallest value FFFFh = Highest possible value |
15-12 | FEATUREVER | R | 7h | Feature Set for the module *instance*
0h = Smallest value Fh = Highest possible value |
11-8 | INSTNUM | R | 0h | Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0h = Smallest value Fh = Highest possible value |
7-4 | MAJREV | R | 1h | Major rev of the IP
0h = Smallest value Fh = Highest possible value |
3-0 | MINREV | R | 0h | Minor rev of the IP
0h = Smallest value Fh = Highest possible value |
CRCCTRL is shown in Figure 14-6 and described in Table 14-9.
Return to the Summary Table.
CRC Control Register. Configuration control of the CRC.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OUTPUT_BYTESWAP | RESERVED | INPUT_ENDIANNESS | BITREVERSE | POLYSIZE | ||
R-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | OUTPUT_BYTESWAP | R/W | 0h | CRC Output Byteswap Enable. This bit controls whether the output is byte-swapped upon a read of the CRCOUT register. If CRCOUT is accessed as a half-word, and the OUTPUT_BYTESWAP is set to 1, then the two bytes in the 16-bit access are swapped and returned. B1 is returned as B0 B0 is returned as B1 If CRCOUT is accessed as a word, and the OUTPUT_BYTESWAP is set to 1, then the four bytes in the 32-bit read are swapped. B3 is returned as B0 B2 is returned as B1 B1 is returned as B2 B0 is returned as B3 Note that if the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP enabled, then the output is: MSB LSB 0x0 0x0 B0 B1 If the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP disabled, then the output is: MSB LSB 0x0 0x0 B1 B0 0h = Output byteswapping is disabled 1h = Output byteswapping is enabled. |
3 | RESERVED | R | 0h | Reserved |
2 | INPUT_ENDIANNESS | R/W | 0h | CRC Endian. This bit indicates the byte order within a word or half word of input data.
0h = LSB is lowest memory address and first to be processed. 1h = LSB is highest memory address and last to be processed. |
1 | BITREVERSE | R/W | 0h | CRC Bit Input and output Reverse. This bit indicates that the bit order of each input byte used for the CRC calculation is reversed before it is passed to the generator, and that the bit order of the calculated CRC is be reversed when read from CRC_RESULT.
0h = Bit order is not reversed. 1h = Bit order is reversed. |
0 | POLYSIZE | R/W | 0h | This bit indicates which CRC calculation is performed by the generator.
0h = CRC-32 ISO-3309 calculation is performed 1h = CRC-16 CCITT is performed |
CRCSEED is shown in Figure 14-7 and described in Table 14-10.
Return to the Summary Table.
CRC Seed Register. The Data written to this register is used to initialize the CRC result with this SEED value. Note that in 16-bit mode only the lower 16-bits of this value are used. After writing this register the CRC Output Result Register will reflect this value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEED | |||||||||||||||||||||||||||||||
W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SEED | W | 0h | Seed Data
00000000h = Minimum value FFFFFFFFh = Maximum value |
CRCIN is shown in Figure 14-8 and described in Table 14-11.
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CRC Input Data Register. The Data written to this register is used along with the current CRC result to calculate the next CRC result. This is done in a single clock cycle and requires no wait states. This register can by written as a byte, half word or word transfer and the correct number of bits will be used for the next CRC result.
This register is also mapped to a range of registers starting at 0xTDB_X000 and ending at 0xTDB_XFFF to allow memcpy to be used instead of DMA for CRC calculations that do not exceed the bounds of the memory range of this register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | W | 0h | Input Data
00000000h = Minimum value FFFFFFFFh = Maximum value |
CRCOUT is shown in Figure 14-9 and described in Table 14-12.
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CRC Output Result Register. This register stores the result of the current CRC calculation. Note when configured for 16-bit mode the upper bits will read back 0. Note that if output inversion is set in the CRC Control register it will be applied.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESULT | R | 0h | Result
00000000h = Minimum value FFFFFFFFh = Maximum value |
CRCIN_IDX[y] is shown in Figure 14-10 and described in Table 14-13.
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This register is dual mapped to CRCIN and is intended to allow operation with C memcpy routine.
Offset = 1800h + (y * 4h); where y = 0h to 1FFh
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
HW-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | HW | 0h | Input Data
00000000h = Minimum value FFFFFFFFh = Maximum value |