SLAU893B October   2023  – July 2024 MSPM0C1103 , MSPM0C1104

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
    5. 1.5 NONMAIN_C1103_C1104 Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 Peripheral Power Enable Control
        1. 2.2.6.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.1.1 SYSOSC FCL in Internal Resistor Mode
          2. 2.3.1.2.2 Disabling SYSOSC
        3. 2.3.1.3 LFCLK_IN (Digital Clock)
        4. 2.3.1.4 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1 MCLK (Main Clock) Tree
        2. 2.3.2.2 CPUCLK (Processor Clock)
        3. 2.3.2.3 ULPCLK (Low-Power Clock)
        4. 2.3.2.4 MFCLK (Middle Frequency Clock)
        5. 2.3.2.5 LFCLK (Low-Frequency Clock)
        6. 2.3.2.6 ADCCLK (ADC Sample Period Clock)
        7. 2.3.2.7 External Clock Output (CLK_OUT)
        8. 2.3.2.8 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 MCLK Monitor
        2. 2.3.4.2 Startup Monitors
          1. 2.3.4.2.1 LFOSC Startup Monitor
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Shutdown Mode Handling
      7. 2.4.7  Configuration Lockout
      8. 2.4.8  System Status
      9. 2.4.9  Error Handling
      10. 2.4.10 SYSCTL Events
        1. 2.4.10.1 CPU Interrupt Event (CPU_INT)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Optimizing for Lowest Wakeup Latency
      6. 2.5.6 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL_C1103_C1104 Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 NVM (Flash)
    1. 5.1 NVM Overview
      1. 5.1.1 Key Features
      2. 5.1.2 System Components
      3. 5.1.3 Terminology
    2. 5.2 Flash Memory Bank Organization
      1. 5.2.1 Banks
      2. 5.2.2 Flash Memory Regions
      3. 5.2.3 Addressing
        1. 5.2.3.1 Flash Memory Map
      4. 5.2.4 Memory Organization Examples
    3. 5.3 Flash Controller
      1. 5.3.1 Overview of Flash Controller Commands
      2. 5.3.2 NOOP Command
      3. 5.3.3 PROGRAM Command
        1. 5.3.3.1 Program Bit Masking Behavior
        2. 5.3.3.2 Programming Less Than One Flash Word
        3. 5.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 5.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 5.3.3.5 Executing a PROGRAM Operation
      4. 5.3.4 ERASE Command
        1. 5.3.4.1 Erase Sector Masking Behavior
        2. 5.3.4.2 Executing an ERASE Operation
      5. 5.3.5 READVERIFY Command
        1. 5.3.5.1 Executing a READVERIFY Operation
      6. 5.3.6 BLANKVERIFY Command
        1. 5.3.6.1 Executing a BLANKVERIFY Operation
      7. 5.3.7 Command Diagnostics
        1. 5.3.7.1 Command Status
        2. 5.3.7.2 Address Translation
        3. 5.3.7.3 Pulse Counts
      8. 5.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 5.3.9 FLASHCTL Events
        1. 5.3.9.1 CPU Interrupt Event Publisher
    4. 5.4 Write Protection
      1. 5.4.1 Write Protection Resolution
      2. 5.4.2 Static Write Protection
      3. 5.4.3 Dynamic Write Protection
        1. 5.4.3.1 Configuring Protection for the MAIN Region
        2. 5.4.3.2 Configuring Protection for the NONMAIN Region
    5. 5.5 Read Interface
      1. 5.5.1 Bank Address Swapping
    6. 5.6 FLASHCTL Registers
  8. 6 Events
    1. 6.1 Events Overview
      1. 6.1.1 Event Publisher
      2. 6.1.2 Event Subscriber
      3. 6.1.3 Event Fabric Routing
        1. 6.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 6.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 6.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 6.1.4 Event Routing Map
      5. 6.1.5 Event Propagation Latency
    2. 6.2 Events Operation
      1. 6.2.1 CPU Interrupt
      2. 6.2.2 DMA Trigger
      3. 6.2.3 Peripheral to Peripheral Event
      4. 6.2.4 Extended Module Description Register
      5. 6.2.5 Using Event Registers
        1. 6.2.5.1 Event Registers
        2. 6.2.5.2 Configuring Events
        3. 6.2.5.3 Responding to CPU Interrupts in Application Software
        4. 6.2.5.4 Hardware Event Handling
  9. 7 IOMUX
    1. 7.1 IOMUX Overview
      1. 7.1.1 IO Types and Analog Sharing
    2. 7.2 IOMUX Operation
      1. 7.2.1 Peripheral Function (PF) Assignment
      2. 7.2.2 Logic High to Hi-Z Conversion
      3. 7.2.3 Logic Inversion
      4. 7.2.4 SHUTDOWN Mode Wakeup Logic
      5. 7.2.5 Pullup/Pulldown Resistors
      6. 7.2.6 Drive Strength Control
      7. 7.2.7 Hysteresis and Logic Level Control
    3. 7.3 IOMUX (PINCMx) Register Format
    4. 7.4 IOMUX Registers
  10. 8 GPIO
    1. 8.1 GPIO Overview
    2. 8.2 GPIO Operation
      1. 8.2.1 GPIO Ports
      2. 8.2.2 GPIO Read/Write Interface
      3. 8.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 8.2.4 GPIO Fast Wake
      5. 8.2.5 GPIO DMA Interface
      6. 8.2.6 Event Publishers and Subscribers
    3. 8.3 GPIO Registers
  11. 9 ADC
    1. 9.1 ADC Overview
    2. 9.2 ADC Operation
      1. 9.2.1  ADC Core
      2. 9.2.2  Voltage Reference Options
      3. 9.2.3  Generic Resolution Modes
      4. 9.2.4  Hardware Averaging
      5. 9.2.5  ADC Clocking
      6. 9.2.6  Common ADC Use Cases
      7. 9.2.7  Power Down Behavior
      8. 9.2.8  Sampling Trigger Sources and Sampling Modes
        1. 9.2.8.1 AUTO Sampling Mode
        2. 9.2.8.2 MANUAL Sampling Mode
      9. 9.2.9  Sampling Period
      10. 9.2.10 Conversion Modes
      11. 9.2.11 Data Format
      12. 9.2.12 Advanced Features
        1. 9.2.12.1 Window Comparator
        2. 9.2.12.2 DMA and FIFO Operation
        3. 9.2.12.3 Analog Peripheral Interconnection
      13. 9.2.13 Status Register
      14. 9.2.14 ADC Events
        1. 9.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 9.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 9.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 9.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 9.3 ADC0 Registers
  12. 10VREF
    1. 10.1 VREF Overview
    2. 10.2 VREF Operation
      1. 10.2.1 Internal Reference Generation
    3. 10.3 VREF Registers
  13. 11UART
    1. 11.1 UART Overview
      1. 11.1.1 Purpose of the Peripheral
      2. 11.1.2 Features
      3. 11.1.3 Functional Block Diagram
    2. 11.2 UART Operation
      1. 11.2.1 Clock Control
      2. 11.2.2 Signal Descriptions
      3. 11.2.3 General Architecture and Protocol
        1. 11.2.3.1  Transmit Receive Logic
        2. 11.2.3.2  Bit Sampling
        3. 11.2.3.3  Majority Voting Feature
        4. 11.2.3.4  Baud Rate Generation
        5. 11.2.3.5  Data Transmission
        6. 11.2.3.6  Error and Status
        7. 11.2.3.7  Local Interconnect Network (LIN) Support
          1. 11.2.3.7.1 LIN Responder Transmission Delay
        8. 11.2.3.8  Flow Control
        9. 11.2.3.9  Idle-Line Multiprocessor
        10. 11.2.3.10 9-Bit UART Mode
        11. 11.2.3.11 RS485 Support
        12. 11.2.3.12 DALI Protocol
        13. 11.2.3.13 Manchester Encoding and Decoding
        14. 11.2.3.14 IrDA Encoding and Decoding
        15. 11.2.3.15 ISO7816 Smart Card Support
        16. 11.2.3.16 Address Detection
        17. 11.2.3.17 FIFO Operation
        18. 11.2.3.18 Loopback Operation
        19. 11.2.3.19 Glitch Suppression
      4. 11.2.4 Low Power Operation
      5. 11.2.5 Reset Considerations
      6. 11.2.6 Initialization
      7. 11.2.7 Interrupt and Events Support
        1. 11.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 11.2.8 Emulation Modes
    3. 11.3 UART0 Registers
  14. 12SPI
    1. 12.1 SPI Overview
      1. 12.1.1 Purpose of the Peripheral
      2. 12.1.2 Features
      3. 12.1.3 Functional Block Diagram
      4. 12.1.4 External Connections and Signal Descriptions
    2. 12.2 SPI Operation
      1. 12.2.1 Clock Control
      2. 12.2.2 General Architecture
        1. 12.2.2.1 Chip Select and Command Handling
          1. 12.2.2.1.1 Chip Select Control
          2. 12.2.2.1.2 Command Data Control
        2. 12.2.2.2 Data Format
        3. 12.2.2.3 Delayed data sampling
        4. 12.2.2.4 Clock Generation
        5. 12.2.2.5 FIFO Operation
        6. 12.2.2.6 Loopback mode
        7. 12.2.2.7 DMA Operation
        8. 12.2.2.8 Repeat Transfer mode
        9. 12.2.2.9 Low Power Mode
      3. 12.2.3 Protocol Descriptions
        1. 12.2.3.1 Motorola SPI Frame Format
        2. 12.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 12.2.4 Reset Considerations
      5. 12.2.5 Initialization
      6. 12.2.6 Interrupt and Events Support
        1. 12.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 12.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 12.2.7 Emulation Modes
    3. 12.3 SPI Registers
  15. 13I2C
    1. 13.1 I2C Overview
      1. 13.1.1 Purpose of the Peripheral
      2. 13.1.2 Features
      3. 13.1.3 Functional Block Diagram
      4. 13.1.4 Environment and External Connections
    2. 13.2 I2C Operation
      1. 13.2.1 Clock Control
        1. 13.2.1.1 Clock Select and I2C Speed
        2. 13.2.1.2 Clock Startup
      2. 13.2.2 Signal Descriptions
      3. 13.2.3 General Architecture
        1. 13.2.3.1  I2C Bus Functional Overview
        2. 13.2.3.2  START and STOP Conditions
        3. 13.2.3.3  Data Format with 7-Bit Address
        4. 13.2.3.4  Acknowledge
        5. 13.2.3.5  Repeated Start
        6. 13.2.3.6  SCL Clock Low Timeout
        7. 13.2.3.7  Clock Stretching
        8. 13.2.3.8  Dual Address
        9. 13.2.3.9  Arbitration
        10. 13.2.3.10 Multiple Controller Mode
        11. 13.2.3.11 Glitch Suppression
        12. 13.2.3.12 FIFO operation
          1. 13.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 13.2.3.13 Loopback mode
        14. 13.2.3.14 Burst Mode
        15. 13.2.3.15 DMA Operation
        16. 13.2.3.16 Low-Power Operation
      4. 13.2.4 Protocol Descriptions
        1. 13.2.4.1 I2C Controller Mode
          1. 13.2.4.1.1 Controller Configuration
          2. 13.2.4.1.2 Controller Mode Operation
          3. 13.2.4.1.3 Read On TX Empty
        2. 13.2.4.2 I2C Target Mode
          1. 13.2.4.2.1 Target Mode Operation
      5. 13.2.5 Reset Considerations
      6. 13.2.6 Initialization
      7. 13.2.7 Interrupt and Events Support
        1. 13.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 13.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 13.2.8 Emulation Modes
    3. 13.3 I2C Registers
  16. 14CRC
    1. 14.1 CRC Overview
      1. 14.1.1 CRC16-CCITT
    2. 14.2 CRC Operation
      1. 14.2.1 CRC Generator Implementation
      2. 14.2.2 Configuration
        1. 14.2.2.1 Bit Order
        2. 14.2.2.2 Byte Swap
        3. 14.2.2.3 Byte Order
        4. 14.2.2.4 CRC C Library Compatibility
    3. 14.3 CRC Registers
  17. 15Timers (TIMx)
    1. 15.1 TIMx Overview
      1. 15.1.1 TIMG Overview
        1. 15.1.1.1 TIMG Features
        2. 15.1.1.2 Functional Block Diagram
      2. 15.1.2 TIMA Overview
        1. 15.1.2.1 TIMA Features
        2. 15.1.2.2 Functional Block Diagram
      3. 15.1.3 TIMx Instance Configuration
    2. 15.2 TIMx Operation
      1. 15.2.1  Timer Counter
        1. 15.2.1.1 Clock Source Select and Prescaler
          1. 15.2.1.1.1 Internal Clock and Prescaler
          2. 15.2.1.1.2 External Signal Trigger
        2. 15.2.1.2 Repeat Counter (TIMA only)
      2. 15.2.2  Counting Mode Control
        1. 15.2.2.1 One-shot and Periodic Modes
        2. 15.2.2.2 Down Counting Mode
        3. 15.2.2.3 Up/Down Counting Mode
        4. 15.2.2.4 Up Counting Mode
        5. 15.2.2.5 Phase Load (TIMA only)
      3. 15.2.3  Capture/Compare Module
        1. 15.2.3.1 Capture Mode
          1. 15.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 15.2.3.1.1.1 CCP Input Edge Synchronization
            2. 15.2.3.1.1.2 CCP Input Pulse Conditions
            3. 15.2.3.1.1.3 Counter Control Operation
            4. 15.2.3.1.1.4 CCP Input Filtering
            5. 15.2.3.1.1.5 Input Selection
          2. 15.2.3.1.2 Use Cases
            1. 15.2.3.1.2.1 Edge Time Capture
            2. 15.2.3.1.2.2 Period Capture
            3. 15.2.3.1.2.3 Pulse Width Capture
            4. 15.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 15.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 15.2.3.1.3.1 QEI With 2-Signal
            2. 15.2.3.1.3.2 QEI With Index Input
            3. 15.2.3.1.3.3 QEI Error Detection
          4. 15.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 15.2.3.2 Compare Mode
          1. 15.2.3.2.1 Edge Count
      4. 15.2.4  Shadow Load and Shadow Compare
        1. 15.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 15.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 15.2.5  Output Generator
        1. 15.2.5.1 Configuration
        2. 15.2.5.2 Use Cases
          1. 15.2.5.2.1 Edge-Aligned PWM
          2. 15.2.5.2.2 Center-Aligned PWM
          3. 15.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 15.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 15.2.5.3 Forced Output
      6. 15.2.6  Fault Handler (TIMA only)
        1. 15.2.6.1 Fault Input Conditioning
        2. 15.2.6.2 Fault Input Sources
        3. 15.2.6.3 Counter Behavior With Fault Conditions
        4. 15.2.6.4 Output Behavior With Fault Conditions
      7. 15.2.7  Synchronization With Cross Trigger
        1. 15.2.7.1 Main Timer Cross Trigger Configuration
        2. 15.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 15.2.8  Low Power Operation
      9. 15.2.9  Interrupt and Event Support
        1. 15.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 15.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 15.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 15.2.10 Debug Handler (TIMA Only)
    3. 15.3 TIMx Registers
  18. 16WWDT
    1. 16.1 WWDT Overview
      1. 16.1.1 Watchdog Mode
      2. 16.1.2 Interval Timer Mode
    2. 16.2 WWDT Operation
      1. 16.2.1 Mode Selection
      2. 16.2.2 Clock Configuration
      3. 16.2.3 Low-Power Mode Behavior
      4. 16.2.4 Debug Behavior
      5. 16.2.5 WWDT Events
        1. 16.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 16.3 WWDT Registers
  19. 17Debug
    1. 17.1 Overview
      1. 17.1.1 Debug Interconnect
      2. 17.1.2 Physical Interface
      3. 17.1.3 Debug Access Ports
    2. 17.2 Debug Features
      1. 17.2.1 Processor Debug
        1. 17.2.1.1 Breakpoint Unit (BPU)
        2. 17.2.1.2 Data Watchpoint and Trace Unit (DWT)
      2. 17.2.2 Peripheral Debug
      3. 17.2.3 EnergyTrace Technology
    3. 17.3 Behavior in Low Power Modes
    4. 17.4 Restricting Debug Access
    5. 17.5 Mailbox (DSSM)
      1. 17.5.1 DSSM Events
        1. 17.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 17.5.2 DEBUGSS Registers
  20. 18Revision History

9.3 ADC0 Registers

Table 9-10 lists the memory-mapped registers for the ADC0 registers. All register offset addresses not listed in Table 9-10 should be considered as reserved locations and the register contents should not be modified.

Table 9-10 ADC0 Registers
OffsetAcronymRegister NameSection
400hFSUB_0Subscriber Configuration Register.Section 9.3.1
444hFPUB_1Publisher Configuration Register.Section 9.3.2
800hPWRENPower enableSection 9.3.3
804hRSTCTLReset ControlSection 9.3.4
808hCLKCFGADC clock configuration RegisterSection 9.3.5
814hSTATStatus RegisterSection 9.3.6
1028hIMASKInterrupt maskSection 9.3.7
1030hRISRaw interrupt statusSection 9.3.8
1038hMISMasked interrupt statusSection 9.3.9
1040hISETInterrupt setSection 9.3.10
1048hICLRInterrupt clearSection 9.3.11
1058hIMASKInterrupt maskSection 9.3.12
1060hRISRaw interrupt statusSection 9.3.13
1068hMISMasked interrupt statusSection 9.3.14
1070hISETInterrupt setSection 9.3.15
1078hICLRInterrupt clearSection 9.3.16
1088hIMASKInterrupt mask extensionSection 9.3.17
1090hRISRaw interrupt status extensionSection 9.3.18
1098hMISMasked interrupt status extensionSection 9.3.19
10A0hISETInterrupt set extensionSection 9.3.20
10A8hICLRInterrupt clear extensionSection 9.3.21
1100hCTL0Control Register 0Section 9.3.22
1104hCTL1Control Register 1Section 9.3.23
1108hCTL2Control Register 2Section 9.3.24
110ChCTL3Control Register 3Section 9.3.25
1114hSCOMP0Sample Time Compare 0 RegisterSection 9.3.26
1118hSCOMP1Sample Time Compare 1 RegisterSection 9.3.27
111ChREFCFGReference Buffer Configuration RegisterSection 9.3.28
1148hWCLOWWindow Comparator Low Threshold RegisterSection 9.3.29
1150hWCHIGHWindow Comparator High Threshold RegisterSection 9.3.30
1160hFIFODATAFIFO Data RegisterSection 9.3.31
1170hASCRESASC Result RegisterSection 9.3.32
1180h + formulaMEMCTL_yConversion Memory Control RegisterSection 9.3.33
1280h + formulaMEMRES_yMemory Result RegisterSection 9.3.34
1340hSTATUSStatus RegisterSection 9.3.35

Complex bit access types are encoded to fit into small table cells. Table 9-11 shows the codes that are used for access types in this section.

Table 9-11 ADC0 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RHR
H		Read
Set or cleared by hardware
Write Type
WWWrite
WKW
K		Write
Write protected by a key
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

9.3.1 FSUB_0 Register (Offset = 400h) [Reset = 00000000h]

FSUB_0 is shown in Figure 9-5 and described in Table 9-12.

Return to the Table 9-10.

Subscriber port

Figure 9-5 FSUB_0 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDCHANID
R-0hR/W-0h
Table 9-12 FSUB_0 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 255.

9.3.2 FPUB_1 Register (Offset = 444h) [Reset = 00000000h]

FPUB_1 is shown in Figure 9-6 and described in Table 9-13.

Return to the Table 9-10.

Publisher port

Figure 9-6 FPUB_1 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDCHANID
R-0hR/W-0h
Table 9-13 FPUB_1 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 255.

9.3.3 PWREN Register (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 9-7 and described in Table 9-14.

Return to the Table 9-10.

Register to control the power state

Figure 9-7 PWREN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENABLE
R-0hR/WK-0h
Table 9-14 PWREN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to allow Power State Change
26h = KEY to allow write access to this register
23-1RESERVEDR0h
0ENABLER/WK0hEnable the power

#ADC0_PERIPHERALREGION_ULLMEM_EXT_GPRCM_GPRCM_PWREN_KEY must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

9.3.4 RSTCTL Register (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 9-8 and described in Table 9-15.

Return to the Table 9-10.

Register to control reset assertion and de-assertion

Figure 9-8 RSTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESETSTKYCLRRESETASSERT
R-0hWK-0hWK-0h
Table 9-15 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hUnlock key
B1h = KEY to allow write access to this register
23-2RESERVEDR0h
1RESETSTKYCLRWK0hClear the RESETSTKY bit in the STAT register

#ADC0_PERIPHERALREGION_ULLMEM_EXT_GPRCM_GPRCM_RSTCTL_KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0RESETASSERTWK0hAssert reset to the peripheral

#ADC0_PERIPHERALREGION_ULLMEM_EXT_GPRCM_GPRCM_RSTCTL_KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

9.3.5 CLKCFG Register (Offset = 808h) [Reset = 00000000h]

CLKCFG is shown in Figure 9-9 and described in Table 9-16.

Return to the Table 9-10.

ADC clock configuration

Figure 9-9 CLKCFG Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCCONSTOPCCONRUNRESERVEDSAMPCLK
R-0hR/W-0hR/W-0hR-0hR/W-0h
Table 9-16 CLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hUnlock key
A9h = KEY to allow write access to this register
23-6RESERVEDR0h
5CCONSTOPR/W0hCCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source.
0h = ADC conversion clock source is not kept continuously on during STOP mode.
1h = ADC conversion clock source kept continuously on during STOP mode.
4CCONRUNR/W0hCCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source.
0h = ADC conversion clock source is not kept continuously on during RUN mode.
1h = ADC conversion clock source kept continuously on during RUN mode.
3-2RESERVEDR0h
1-0SAMPCLKR/W0hADC sample clock source selection.
0h = ULPCLK is the source of ADC sample clock.
1h = SYSOSC is the source of ADC sample clock.
2h = HFCLK clock is the source of ADC sample clock.
Note : HFCLK may not be available on all the devices.

9.3.6 STAT Register (Offset = 814h) [Reset = 000X0000h]

STAT is shown in Figure 9-10 and described in Table 9-17.

Return to the Table 9-10.

peripheral enable and reset status

Figure 9-10 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-X
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 9-17 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYRXThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0RESERVEDR0h

9.3.7 IMASK Register (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 9-11 and described in Table 9-18.

Return to the Table 9-10.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 9-11 IMASK Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
ASCDONEUVIFGDMADONEINIFGLOWIFGHIGHIFGTOVIFGOVIFG
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-18 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11MEMRESIFG3R/W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7ASCDONER0hMask for ASC done raw interrupt flag
0h = Interrupt is not pending.
1h = Interrupt is pending.
6UVIFGR/W0hRaw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
5DMADONER0hRaw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
4INIFGR/W0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1TOVIFGR/W0hRaw interrupt flag for sequence conversion timeout overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
0OVIFGR/W0hRaw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.

9.3.8 RIS Register (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 9-12 and described in Table 9-19.

Return to the Table 9-10.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 9-12 RIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
ASCDONEUVIFGDMADONEINIFGLOWIFGHIGHIFGTOVIFGOVIFG
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-19 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11MEMRESIFG3R/W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7ASCDONER0hRaw interrupt flag for ASC done
0h = Interrupt is not pending.
1h = Interrupt is pending.
6UVIFGR/W0hRaw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
5DMADONER0hRaw interrupt flag for DMADONE.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
4INIFGR/W0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1TOVIFGR/W0hRaw interrupt flag for sequence conversion trigger overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
0OVIFGR/W0hRaw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.

9.3.9 MIS Register (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 9-13 and described in Table 9-20.

Return to the Table 9-10.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 9-13 MIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
ASCDONEUVIFGDMADONEINIFGLOWIFGHIGHIFGTOVIFGOVIFG
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-20 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11MEMRESIFG3R/W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7ASCDONER0hMasked interrupt status for ASC done
0h = Interrupt is not pending.
1h = Interrupt is pending.
6UVIFGR/W0hRaw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
5DMADONER0hRaw interrupt flag for DMADONE.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
4INIFGR/W0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1TOVIFGR/W0hRaw interrupt flag for sequence conversion timeout overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
0OVIFGR/W0hRaw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.

9.3.10 ISET Register (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 9-14 and described in Table 9-21.

Return to the Table 9-10.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 9-14 ISET Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
ASCDONEUVIFGDMADONEINIFGLOWIFGHIGHIFGTOVIFGOVIFG
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-21 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11MEMRESIFG3R/W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7ASCDONER0hSet ASC done flag in RIS
0h = Interrupt is not pending.
1h = Interrupt is pending.
6UVIFGR/W0hRaw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
5DMADONER0hRaw interrupt flag for DMADONE.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
4INIFGR/W0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1TOVIFGR/W0hRaw interrupt flag for sequence conversion timeout overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
0OVIFGR/W0hRaw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.

9.3.11 ICLR Register (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 9-15 and described in Table 9-22.

Return to the Table 9-10.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 9-15 ICLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
ASCDONEUVIFGDMADONEINIFGLOWIFGHIGHIFGTOVIFGOVIFG
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-22 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11MEMRESIFG3R/W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7ASCDONER0hClear ASC done flag in RIS
0h = Interrupt is not pending.
1h = Interrupt is pending.
6UVIFGR/W0hRaw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
5DMADONER/W0hRaw interrupt flag for DMADONE.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
4INIFGR/W0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1TOVIFGR/W0hRaw interrupt flag for sequence conversion timeout overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
0OVIFGR/W0hRaw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.

9.3.12 IMASK Register (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 9-16 and described in Table 9-23.

Return to the Table 9-10.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 9-16 IMASK Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG0
R-0hR/W-0h
76543210
RESERVEDINIFGLOWIFGHIGHIFGRESERVED
R-0hR/W-0hR/W-0hR/W-0hR-0h
Table 9-23 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDR0h
4INIFGR/W0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDR0h

9.3.13 RIS Register (Offset = 1060h) [Reset = 00000000h]

RIS is shown in Figure 9-17 and described in Table 9-24.

Return to the Table 9-10.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 9-17 RIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG0
R-0hR/W-0h
76543210
RESERVEDINIFGLOWIFGHIGHIFGRESERVED
R-0hR/W-0hR/W-0hR/W-0hR-0h
Table 9-24 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDR0h
4INIFGR/W0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDR0h

9.3.14 MIS Register (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 9-18 and described in Table 9-25.

Return to the Table 9-10.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 9-18 MIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG0
R-0hR/W-0h
76543210
RESERVEDINIFGLOWIFGHIGHIFGRESERVED
R-0hR/W-0hR/W-0hR/W-0hR-0h
Table 9-25 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDR0h
4INIFGR/W0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDR0h

9.3.15 ISET Register (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 9-19 and described in Table 9-26.

Return to the Table 9-10.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 9-19 ISET Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG0
R-0hR/W-0h
76543210
RESERVEDINIFGLOWIFGHIGHIFGRESERVED
R-0hR/W-0hR/W-0hR/W-0hR-0h
Table 9-26 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDR0h
4INIFGR/W0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDR0h

9.3.16 ICLR Register (Offset = 1078h) [Reset = 00000000h]

ICLR is shown in Figure 9-20 and described in Table 9-27.

Return to the Table 9-10.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 9-20 ICLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG0
R-0hR/W-0h
76543210
RESERVEDINIFGLOWIFGHIGHIFGRESERVED
R-0hR/W-0hR/W-0hR/W-0hR-0h
Table 9-27 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDR0h
4INIFGR/W0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDR0h

9.3.17 IMASK Register (Offset = 1088h) [Reset = 00000000h]

IMASK is shown in Figure 9-21 and described in Table 9-28.

Return to the Table 9-10.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 9-21 IMASK Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVED
R-0h
Table 9-28 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11MEMRESIFG3R/W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDR0h

9.3.18 RIS Register (Offset = 1090h) [Reset = 00000000h]

RIS is shown in Figure 9-22 and described in Table 9-29.

Return to the Table 9-10.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 9-22 RIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVED
R-0h
Table 9-29 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11MEMRESIFG3R/W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDR0h

9.3.19 MIS Register (Offset = 1098h) [Reset = 00000000h]

MIS is shown in Figure 9-23 and described in Table 9-30.

Return to the Table 9-10.

Extension of Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 9-23 MIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVED
R-0h
Table 9-30 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11MEMRESIFG3R/W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDR0h

9.3.20 ISET Register (Offset = 10A0h) [Reset = 00000000h]

ISET is shown in Figure 9-24 and described in Table 9-31.

Return to the Table 9-10.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 9-24 ISET Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVED
R-0h
Table 9-31 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11MEMRESIFG3R/W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDR0h

9.3.21 ICLR Register (Offset = 10A8h) [Reset = 00000000h]

ICLR is shown in Figure 9-25 and described in Table 9-32.

Return to the Table 9-10.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 9-25 ICLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVED
R-0h
Table 9-32 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11MEMRESIFG3R/W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDR0h

9.3.22 CTL0 Register (Offset = 1100h) [Reset = 00000000h]

CTL0 is shown in Figure 9-26 and described in Table 9-33.

Return to the Table 9-10.

Control Register 0

Figure 9-26 CTL0 Register
3130292827262524
RESERVEDSCLKDIV
R-0hR/W-0h
2322212019181716
RESERVEDPWRDN
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENC
R-0hRH/W-0h
Table 9-33 CTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR0h
26-24SCLKDIVR/W0hSample clock divider
0h = Do not divide clock source
1h = Divide clock source by 2
2h = Divide clock source by 4
3h = Divide clock source by 8
4h = Divide clock source by 16
5h = Divide clock source by 24
6h = Divide clock source by 32
7h = Divide clock source by 48
23-17RESERVEDR0h
16PWRDNR/W0hPower down policy
0h = ADC is powered down on completion of a conversion if there is no pending trigger
1h = ADC remains powered on as long as it is enabled through software.
15-1RESERVEDR0h
0ENCRH/W0hEnable conversion
0h = Conversion disabled. ENC change from ON to OFF will abort single or repeat sequence on a MEMCTLx boundary. The current conversion will finish and result stored in corresponding MEMRESx.
1h = Conversion enabled. ADC sequencer waits for valid trigger (software or hardware).

9.3.23 CTL1 Register (Offset = 1104h) [Reset = 00000000h]

CTL1 is shown in Figure 9-27 and described in Table 9-34.

Return to the Table 9-10.

Control Register 1

Figure 9-27 CTL1 Register
3130292827262524
RESERVEDAVGDRESERVEDAVGN
R-0hR/W-0hR-0hR/W-0h
2322212019181716
RESERVEDSAMPMODERESERVEDCONSEQ
R-0hR/W-0hR-0hR/W-0h
15141312111098
RESERVEDSC
R-0hRH/W-0h
76543210
RESERVEDTRIGSRC
R-0hR/W-0h
Table 9-34 CTL1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0h
30-28AVGDR/W0hHardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropriately result will be truncated.
0h (R/W) = No shift
1h (R/W) = 1 bit shift
2h (R/W) = 2 bit shift
3h (R/W) = 3 bit shift
4h (R/W) = 4 bit shift
5h (R/W) = 5 bit shift
6h (R/W) = 6 bit shift
7h (R/W) = 7 bit shift
27RESERVEDR0h
26-24AVGNR/W0hHardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx.
0h (R/W) = Disables averager
1h (R/W) = Averages 2 conversions before storing in MEMRESx register
2h (R/W) = Averages 4 conversions before storing in MEMRESx register
3h (R/W) = Averages 8 conversions before storing in MEMRESx register
4h (R/W) = Averages 16 conversions before storing in MEMRESx register
5h (R/W) = Averages 32 conversions before storing in MEMRESx register
6h (R/W) = Averages 64 conversions before storing in MEMRESx register
7h (R/W) = Averages 128 conversions before storing in MEMRESx register
23-21RESERVEDR0h
20SAMPMODER/W0hSample mode. This bit selects the source of the sampling signal.
MANUAL option is not valid when TRIGSRC is selected as hardware event trigger.
0h = AUTO
1h = MANUAL
19-18RESERVEDR0h
17-16CONSEQR/W0hConversion sequence mode

0h = ADC channel in MEMCTLx pointed by STARTADD will be converted once

1h = ADC channel sequence pointed by STARTADD and ENDADD will be converted once
2h = ADC channel in MEMCTLx pointed by STARTADD will be converted repeatedly

3h = ADC channel sequence pointed by STARTADD and ENDADD will be converted repeatedly
15-9RESERVEDR0h
8SCRH/W0hStart of conversion

0h = When SAMPMODE is set to MANUAL, clearing this bit will end the sample phase and the conversion phase will start.
When SAMPMODE is set to AUTO, writing 0 has no effect.
1h = When SAMPMODE is set to MANUAL, setting this bit will start the sample phase. Sample phase will last as long as this bit is set.
When SAMPMODE is set to AUTO, setting this bit will trigger the timer based sample time.
7-1RESERVEDR0h
0TRIGSRCR/W0hSample trigger source
0h = Software trigger


1h = Hardware event trigger

9.3.24 CTL2 Register (Offset = 1108h) [Reset = 00000000h]

CTL2 is shown in Figure 9-28 and described in Table 9-35.

Return to the Table 9-10.

Control Register 2

Figure 9-28 CTL2 Register
3130292827262524
RESERVEDENDADD
R-0hR/W-0h
2322212019181716
RESERVEDSTARTADD
R-0hR/W-0h
15141312111098
SAMPCNTFIFOENRESERVEDDMAEN
R/W-0hR/W-0hR-0hRH/W-0h
76543210
RESERVEDRESDF
R-0hR/W-0hR/W-0h
Table 9-35 CTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28-24ENDADDR/W0hSequence end address. These bits select which MEMCTLx is the last one for the sequence mode.
The value of ENDADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
00h = MEMCTL0 is selected as end address of sequence.
01h = MEMCTL1 is selected as end address of sequence.
02h = MEMCTL2 is selected as end address of sequence.
03h = MEMCTL3 is selected as end address of sequence.
23-21RESERVEDR0h
20-16STARTADDR/W0hSequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode.
The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
00h = MEMCTL0 is selected as start address of a sequence or for a single conversion.
01h = MEMCTL1 is selected as start address of a sequence or for a single conversion.
02h = MEMCTL2 is selected as start address of a sequence or for a single conversion.
03h = MEMCTL3 is selected as start address of a sequence or for a single conversion.
15-11SAMPCNTR/W0hNumber of ADC converted samples to be transferred on a DMA trigger
0h = Minimum value
18h = Maximum value
10FIFOENR/W0hEnable FIFO based operation
0h = Disable
1h = Enable
9RESERVEDR0h
8DMAENRH/W0hEnable DMA trigger for data transfer.
Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers.
0h (R/W) = DMA trigger not enabled
1h (R/W) = DMA trigger enabled
7-3RESERVEDR0h
2-1RESR/W0hResolution. These bits define the resolution of ADC conversion result.
Note : A value of 3 defaults to 12-bits resolution.
0h = 12-bits resolution
1h = 10-bits resolution
2h = 8-bits resolution
0DFR/W0hData read-back format. Data is always stored in binary unsigned format.
0h = Digital result reads as Binary Unsigned.
1h = Digital result reads Signed Binary. (2s complement), left aligned.

9.3.25 CTL3 Register (Offset = 110Ch) [Reset = 00000000h]

CTL3 is shown in Figure 9-29 and described in Table 9-36.

Return to the Table 9-10.

Control Register 3. This register is used to configure ADC for ad-hoc single conversion.

Figure 9-29 CTL3 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDASCVRSELRESERVEDASCSTIME
R-0hR/W-0hR-0hR/W-0h
76543210
RESERVEDASCCHSEL
R-0hR/W-0h
Table 9-36 CTL3 Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0h
13-12ASCVRSELR/W0hSelects voltage reference for ASC operation. VEREFM must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
0h = VDDA reference.
1h = EXTREF pin reference.
2h = Internal reference.
11-9RESERVEDR0h
8ASCSTIMER/W0hASC sample time compare value select. This is used to select between SCOMP0 and SCOMP1 registers for ASC operation.
0h = Select SCOMP0
1h = Select SCOMP1
7-5RESERVEDR0h
4-0ASCCHSELR/W0hASC channel select
00h = Selects channel 0
01h = Selects channel 1
02h = Selects channel 2
03h = Selects channel 3
04h = Selects channel 4
05h = Selects channel 5
06h = Selects channel 6
07h = Selects channel 7
08h = Selects channel 8
09h = Selects channel 9
0Ah = Selects channel 10
0Bh = Selects channel 11
0Ch = Selects channel 12
0Dh = Selects channel 13
0Eh = Selects channel 14
0Fh = Selects channel 15
10h = Selects channel 16
11h = Selects channel 17
12h = Selects channel 18
13h = Selects channel 19
14h = Selects channel 20
15h = Selects channel 21
16h = Selects channel 22
17h = Selects channel 23
18h = Selects channel 24
19h = Selects channel 25
1Ah = Selects channel 26
1Bh = Selects channel 27
1Ch = Selects channel 28
1Dh = Selects channel 29
1Eh = Selects channel 30
1Fh = Selects channel 31

9.3.26 SCOMP0 Register (Offset = 1114h) [Reset = 00000000h]

SCOMP0 is shown in Figure 9-30 and described in Table 9-37.

Return to the Table 9-10.

Sample time compare 0 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be 0 to write to this register.

Figure 9-30 SCOMP0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDVAL
R-0hR/W-0h
Table 9-37 SCOMP0 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0h
9-0VALR/W0hSpecifies the number of sample clocks.
When VAL = 0 or 1, number of sample clocks = Sample clock divide value.
When VAL > 1, number of sample clocks = VAL x Sample clock divide value.
Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4).
Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.

9.3.27 SCOMP1 Register (Offset = 1118h) [Reset = 00000000h]

SCOMP1 is shown in Figure 9-31 and described in Table 9-38.

Return to the Table 9-10.

Sample time compare 1 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be 0 to write to this register.

Figure 9-31 SCOMP1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDVAL
R-0hR/W-0h
Table 9-38 SCOMP1 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0h
9-0VALR/W0hSpecifies the number of sample clocks.
When VAL = 0 or 1, number of sample clocks = Sample clock divide value.
When VAL > 1, number of sample clocks = VAL x Sample clock divide value.
Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4).
Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.

9.3.28 REFCFG Register (Offset = 111Ch) [Reset = 00000000h]

REFCFG is shown in Figure 9-32 and described in Table 9-39.

Return to the Table 9-10.

Reference buffer configuration register

Figure 9-32 REFCFG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDIBPROGRESERVEDREFVSELREFEN
R-0hR/W-0hR-0hR/W-0hR/W-0h
Table 9-39 REFCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h
4-3IBPROGR/W0hConfigures reference buffer bias current output value
0h = 1uA
1h = 0.5uA
2h = 2uA
3h = 0.67uA
2RESERVEDR0h
1REFVSELR/W0hConfigures reference buffer output voltage
0h = Reference buffer generates 2.5V output
1h = Reference buffer generates 1.4V output
0REFENR/W0hReference buffer enable
0h = Disable
1h = Enable

9.3.29 WCLOW Register (Offset = 1148h) [Reset = 00000000h]

WCLOW is shown in Figure 9-33 and described in Table 9-40.

Return to the Table 9-10.

Window Comparator Low Threshold Register.
The data format that is used to write and read WCLOW depends on the value of DF bit in CTL2 register.
CTL0.ENC must be 0 to write to this register.
Note: Change in ADC data format or resolution does not reset WCLOW.

Figure 9-33 WCLOW Register
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-0hR/W-0h
Table 9-40 WCLOW Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15-0DATAR/W0hIf DF = 0, unsigned binary format has to be used.
The value based on the resolution has to be right aligned with the MSB on the left.
For 10-bits and 8-bits resolution, unused bits have to be 0s.

If DF = 1, 2s-complement format has to be used.
The value based on the resolution has to be left aligned with the LSB on the right.
For 10-bits and 8-bits resolution, unused bits have to be 0s.

9.3.30 WCHIGH Register (Offset = 1150h) [Reset = 00000000h]

WCHIGH is shown in Figure 9-34 and described in Table 9-41.

Return to the Table 9-10.

Window Comparator High Threshold Register.
The data format that is used to write and read WCHIGH depends on the value of DF bit in CTL2 register.
CTL0.ENC must be 0 to write to this register.
Note: Change in ADC data format or resolution does not reset WCHIGH.

Figure 9-34 WCHIGH Register
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-0hR/W-0h
Table 9-41 WCHIGH Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15-0DATAR/W0hIf DF = 0, unsigned binary format has to be used.
The threshold value has to be right aligned, with the MSB on the left.
For 10-bits and 8-bits resolution, unused bit have to be 0s.

If DF = 1, 2s-complement format has to be used.
The value based on the resolution has to be left aligned with the LSB on the right.
For 10-bits and 8-bits resolution, unused bit have to be 0s.

9.3.31 FIFODATA Register (Offset = 1160h) [Reset = 00000000h]

FIFODATA is shown in Figure 9-35 and described in Table 9-42.

Return to the Table 9-10.

FIFO data register. This is a virtual register used to do read from FIFO.

Figure 9-35 FIFODATA Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
Table 9-42 FIFODATA Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hRead from this data field returns the ADC sample from FIFO.

9.3.32 ASCRES Register (Offset = 1170h) [Reset = 00000000h]

ASCRES is shown in Figure 9-36 and described in Table 9-43.

Return to the Table 9-10.

ASC result register

Figure 9-36 ASCRES Register
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-0hR-0h
Table 9-43 ASCRES Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15-0DATAR0hResult of ADC ad-hoc single conversion.
If DF = 0, unsigned binary:
The conversion result is right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion result is left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.

9.3.33 MEMCTL_y Register (Offset = 1180h + formula) [Reset = 00000000h]

MEMCTL_y is shown in Figure 9-37 and described in Table 9-44.

Return to the Table 9-10.

Conversion Memory Control Register.
CTL0.ENC must be 0 to write to this register.

Offset = 1180h + (y * 4h); where y = 0h to 17h

Figure 9-37 MEMCTL_y Register
3130292827262524
RESERVEDWINCOMPRESERVEDTRIG
R-0hR/W-0hR-0hR/W-0h
2322212019181716
RESERVEDBCSENRESERVEDAVGEN
R-0hR/W-0hR-0hR/W-0h
15141312111098
RESERVEDSTIMERESERVEDVRSEL
R-0hR/W-0hR-0hR/W-0h
76543210
RESERVEDCHANSEL
R-0hR/W-0h
Table 9-44 MEMCTL_y Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28WINCOMPR/W0hEnable window comparator.
0h = Disable
1h = Enable
27-25RESERVEDR0h
24TRIGR/W0hTrigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
0h = Next conversion is automatic
1h = Next conversion requires a trigger
23-21RESERVEDR0h
20BCSENR/W0hEnable burn out current source.
0h = Disable
1h = Enable
19-17RESERVEDR0h
16AVGENR/W0hEnable hardware averaging.
0h (R/W) = Averaging disabled.
1h = Averaging enabled.
15-13RESERVEDR0h
12STIMER/W0hSelects the source of sample timer period between SCOMP0 and SCOMP1.
0h = Select SCOMP0
1h = Select SCOMP1
11-10RESERVEDR0h
9-8VRSELR/W0hVoltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
0h = VDDA reference
1h = External reference from pin
2h = Internal reference
7-5RESERVEDR0h
4-0CHANSELR/W0hInput channel select.
00h = Selects channel 0
01h = Selects channel 1
02h = Selects channel 2
03h = Selects channel 3
04h = Selects channel 4
05h = Selects channel 5
06h = Selects channel 6
07h = Selects channel 7
08h = Selects channel 8
09h = Selects channel 9
0Ah = Selects channel 10
0Bh = Selects channel 11
0Ch = Selects channel 12
0Dh = Selects channel 13
0Eh = Selects channel 14
0Fh = Selects channel 15
10h = Selects channel 16
11h = Selects channel 17
12h = Selects channel 18
13h = Selects channel 19
14h = Selects channel 20
15h = Selects channel 21
16h = Selects channel 22
17h = Selects channel 23
18h = Selects channel 24
19h = Selects channel 25
1Ah = Selects channel 26
1Bh = Selects channel 27
1Ch = Selects channel 28
1Dh = Selects channel 29
1Eh = Selects channel 30
1Fh = Selects channel 31

9.3.34 MEMRES_y Register (Offset = 1280h + formula) [Reset = 00000000h]

MEMRES_y is shown in Figure 9-38 and described in Table 9-45.

Return to the Table 9-10.

Memory Result Register

Offset = 1280h + (y * 4h); where y = 0h to 17h

Figure 9-38 MEMRES_y Register
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-0hR-0h
Table 9-45 MEMRES_y Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15-0DATAR0hMEMRES result register.
If DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.

9.3.35 STATUS Register (Offset = 1340h) [Reset = 00000000h]

STATUS is shown in Figure 9-39 and described in Table 9-46.

Return to the Table 9-10.

Status Register

Figure 9-39 STATUS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDASCACTREFBUFRDYBUSY
R-0hR-0hR-0hR-0h
Table 9-46 STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2ASCACTR0hASC active
0h = Idle or done
1h = ASC active
1REFBUFRDYR0hIndicates reference buffer is powered up and ready.
0h = Not ready
1h = Ready
0BUSYR0hBusy. This bit indicates that an active ADC sample or conversion operation is in progress.
0h = No ADC sampling or conversion in progress.
1h = ADC sampling or conversion is in progress.