SLAU893B October 2023 – July 2024 MSPM0C1103 , MSPM0C1104
Table 10-1 lists the memory-mapped registers for the VREF registers. All register offset addresses not listed in Table 10-1 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
800h | PWREN | Power enable | Section 10.3.1 |
804h | RSTCTL | Reset Control | Section 10.3.2 |
814h | STAT | Status Register | Section 10.3.3 |
1000h | CLKDIV | Clock Divider | Section 10.3.4 |
1008h | CLKSEL | Clock Selection | Section 10.3.5 |
1100h | CTL0 | Control 0 | Section 10.3.6 |
1104h | CTL1 | Control 1 | Section 10.3.7 |
1108h | CTL2 | Control 2 | Section 10.3.8 |
Complex bit access types are encoded to fit into small table cells. Table 10-2 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
K | K | Write protected by a key |
W | W | Write |
WK | W K | Write Write protected by a key |
Reset or Default Value | ||
-n | Value after reset or the default value |
PWREN is shown in Figure 10-2 and described in Table 10-3.
Return to the Table 10-1.
Register to control the power state
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R-0h | K-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | X | KEY to allow Power State Change
26h = KEY to allow write access to this register |
23-1 | RESERVED | R | 0h | |
0 | ENABLE | K | X | Enable the power #VREF_PERIPHERALREGION_EXT_GPRCM_GPRCM_PWREN_KEY must be set to 26h to write to this bit. 0h = Disable Power 1h = Enable Power |
RSTCTL is shown in Figure 10-3 and described in Table 10-4.
Return to the Table 10-1.
Register to control reset assertion and de-assertion
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETSTKYCLR | RESETASSERT | |||||
R-0h | WK-X | WK-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | X | Unlock key
B1h = KEY to allow write access to this register |
23-2 | RESERVED | R | 0h | |
1 | RESETSTKYCLR | WK | X | Clear the RESETSTKY bit in the STAT register #VREF_PERIPHERALREGION_EXT_GPRCM_GPRCM_RSTCTL_KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Clear reset sticky bit |
0 | RESETASSERT | WK | X | Assert reset to the peripheral #VREF_PERIPHERALREGION_EXT_GPRCM_GPRCM_RSTCTL_KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Assert reset |
STAT is shown in Figure 10-4 and described in Table 10-5.
Return to the Table 10-1.
peripheral enable and reset status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESETSTKY | ||||||
R-0h | R-X | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | |
16 | RESETSTKY | R | X | This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 1h = The peripheral was reset since the last bit clear |
15-0 | RESERVED | R | 0h |
CLKDIV is shown in Figure 10-5 and described in Table 10-6.
Return to the Table 10-1.
Clock Divider
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RATIO | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | |
2-0 | RATIO | R/W | 0h | Selects divide ratio of module clock to be used in sample and hold logic |
CLKSEL is shown in Figure 10-6 and described in Table 10-7.
Return to the Table 10-1.
Clock Selection
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BUSCLK_SEL | MFCLK_SEL | LFCLK_SEL | RESERVED | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | BUSCLK_SEL | R/W | 0h | Selects BUSCLK as clock source if enabled |
2 | MFCLK_SEL | R/W | 0h | Selects MFCLK as clock source if enabled |
1 | LFCLK_SEL | R/W | 0h | Selects LFCLK as clock source if enabled |
0 | RESERVED | R | 0h |
CTL0 is shown in Figure 10-7 and described in Table 10-8.
Return to the Table 10-1.
Control 0 register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SHMODE | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUFCONFIG | RESERVED | ENABLE | |||||
R/W-0h | R-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | |
8 | SHMODE | R/W | 0h | This bit enable sample and hold mode
0h = Sample and hold mode is disable 1h = Sample and hold mode is enable |
7 | BUFCONFIG | R/W | 0h | These bits configure output buffer.
0h = output 2p5v : Configure Output Buffer to 2.5v 1h = output 1p4v : Configure Output Buffer to 1.4v |
6-1 | RESERVED | R | 0h | |
0 | ENABLE | R/W | 0h | This bit enables the VREF module.
0h = VREF is disabled 1h = VREF is enabled |
CTL1 is shown in Figure 10-8 and described in Table 10-9.
Return to the Table 10-1.
Control 1 register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | READY | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | |
1 | VREFLOSEL | R/W | 0h | This bit select VREFLO pin |
0 | READY | R | 0h | These bits defines status of VREF
0h = VREF output is not ready 1h = VREF output is ready |
CTL2 is shown in Figure 10-9 and described in Table 10-10.
Return to the Table 10-1.
Control 2 register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HCYCLE | SHCYCLE | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | HCYCLE | R/W | 0h | Hold cycle count Total cycles of module clock for hold phase when VREF is working in sample and hold mode in STANDBY to save power. Please refer VREF section of data sheet for recommended values of sample and hold times. 0h = smallest hold cycle FFFFh = largest hold cycle |
15-0 | SHCYCLE | R/W | 0h | Sample and Hold cycle count Total cycles of module clock for sample and hold phase when VREF is working in sample and hold mode in STANDBY to save power. This field should be greater than HCYCLE field. The difference between this field and HCYCLE gives the number of cycles of sample phase. Please refer VREF section of data sheet for recommended values of sample and hold times. 0h = smallest sample and hold cycle count FFFFh = largest sample and hold cycle |