SLAU893B October 2023 – July 2024 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1
The ADC peripheral clock (ADCCLK) is provided by the Section 2.4 and is used for both sampling and conversion. SYSOSC , HFCLK and ULPCLK are the available clock sources available for ADCCLK, which can support up to 24Mhz. Refer to the device-specific data sheet for supported ADCCLK frequencies. Using the ULPCLK, which is the bus clock for all peripherals, is very useful for deterministic start of sampling. The ADC clock source can be selected by programming the SAMPCLK bits in the CLKCFG register.
SYSOSC needs to be active for the ADC to operate properly. If SYSOSC is not running and the ADC is triggered, the ADC will automatically request SYSCTL to enable and set SYSOSC to base frequency during the conversion. If SYSOSC is already enabled, it will remain the same frequency. The only exception to this is in STOP1 operating mode where SYSOSC will go to base frequency when the ADC is triggered.
In order to provide a way to ensure predictable sample rate operation between power modes, the CCONRUN and CCONSTOP bits can be set to signal the ADC that it can expect that the SYSOSC will already be ON when the device is in RUN and STOP modes respectively. When these bits are set, the ADC will not wait for an ACK from SYSCTL to make sure SYSOSC is running before starting sampling. This feature gives users the flexibility to save power in applications where deterministic sample timing is not a requirement. Refer to Section 9.2.6 for examples on how to properly use the CCONRUN and CCONSTOP control bits.
The user must configure the FRANGE bits in the CLKFREQ register to the appropriate setting based on the expected ADCCLK frequency. See the following table for more details on how to properly configure the CLKFREQ register.
CLKFREQ.FRANGE Values | ADCCLK Frequency Range (MHz) |
---|---|
0 | >1 to 4 |
1 | >4 to 8 |
2 | >8 to 16 |
3 | >16 to 20 |
4 | >20 to 24 |