Edge time capture measures the time (in TIMCLK cycles) from the start of the capture operation to the signal edge. The counter is loaded when TIMx is enabled and counts with each TIMCLK period until the CCP edge is detected, which triggers
the capture of the timer value and generates a capture event. The capture edge time is equivalent to the difference between the starting value of the counter and the capture value in TIMx.CC_xy[0/1] register.
Edge Time Capture Configuration
- Set the TIMx.LOAD value.
- In the CTRCTL register, set the desired counter control settings for:
- Counting mode (CM) and counter value after enable (CVAE) (see as described in Section 15.2.2)
- Zero (CZC), advance (CAC), and load control (CLC) to specify what condition controls zeroing, advancing, or loading the counter
- Repeat or one-shot mode (REPEAT)
- Set TIMx.CCCTL_xy[0/1].COC = 1 for capture mode.
- Configure CCP as an input for the CC block by setting respective bit in the CCPD registers. For instance, if TIMx Channel 0 is an input, set CCPD.C0CCP0 = 0.
- For the corresponding CC block control register (CCCTL_01[0/1]), set CCOND to the corresponding setting to capture events based off the input signal condition (rising and/or falling edge). Additionally, set ZCOND or LCOND depending on
the counting mode used.
- Configure input capture settings in the TIMx.IFCTL_xy[0/1] register as described in Section 15.2.3.1.1.
- Enable the counter by setting EN = 1 or waiting for a capture event to occur from the input edge.
Example using up-counting mode for rising edge capture
In up-counting mode starting from zero (CM = 2, CVAE = 2), TIMx can be configured to generate a zero pulse and start the counter from the configured capture event (CCOND) by setting ZCOND to 1.
The expected internal timing for a rising or positive edge time capture in up-counting mode is shown in Figure 15-14.