SLAU893B
October 2023 – July 2024
MSPM0C1103
,
MSPM0C1103-Q1
,
MSPM0C1104
,
MSPM0C1104-Q1
1
Read This First
About This Manual
Notational Conventions
Glossary
Related Documentation
Support Resources
Trademarks
1
Architecture
1.1
Architecture Overview
1.2
Bus Organization
1.3
Platform Memory Map
1.3.1
Code Region
1.3.2
SRAM Region
1.3.3
Peripheral Region
1.3.4
Subsystem Region
1.3.5
System PPB Region
1.4
Boot Configuration
1.4.1
Configuration Memory (NONMAIN)
1.4.1.1
CRC-Backed Configuration Data
1.4.1.2
16-bit Pattern Match for Critical Fields
1.4.2
Boot Configuration Routine (BCR)
1.4.2.1
Serial Wire Debug Related Policies
1.4.2.1.1
SWD Security Level 0
1.4.2.1.2
SWD Security Level 1
1.4.2.1.3
SWD Security Level 2
1.4.2.2
SWD Factory Reset Commands
1.4.2.3
Flash Memory Protection and Integrity Related Policies
1.4.2.3.1
Locking the Application (MAIN) Flash Memory
1.4.2.3.2
Locking the Configuration (NONMAIN) Flash Memory
1.4.2.3.3
Static Write Protection NONMAIN Fields
1.5
NONMAIN_C1103_C1104 Registers
1.6
Factory Constants
1.6.1
FACTORYREGION Registers
2
PMCU
2.1
PMCU Overview
2.1.1
Power Domains
2.1.2
Operating Modes
2.1.2.1
RUN Mode
2.1.2.2
SLEEP Mode
2.1.2.3
STOP Mode
2.1.2.4
STANDBY Mode
2.1.2.5
SHUTDOWN Mode
2.1.2.6
Supported Functionality by Operating Mode
2.1.2.7
Suspended Low-Power Mode Operation
2.2
Power Management (PMU)
2.2.1
Power Supply
2.2.2
Core Regulator
2.2.3
Supply Supervisors
2.2.3.1
Power-on Reset (POR) Supervisor
2.2.3.2
Brownout Reset (BOR) Supervisor
2.2.3.3
POR and BOR Behavior During Supply Changes
2.2.4
Bandgap Reference
2.2.5
Temperature Sensor
2.2.6
Peripheral Power Enable Control
2.2.6.1
Automatic Peripheral Disable in Low Power Modes
2.3
Clock Module (CKM)
2.3.1
Oscillators
2.3.1.1
Internal Low-Frequency Oscillator (LFOSC)
2.3.1.2
Internal System Oscillator (SYSOSC)
2.3.1.2.1
SYSOSC Frequency Correction Loop
2.3.1.2.1.1
SYSOSC FCL in Internal Resistor Mode
2.3.1.2.2
Disabling SYSOSC
2.3.1.3
LFCLK_IN (Digital Clock)
2.3.1.4
HFCLK_IN (Digital clock)
2.3.2
Clocks
2.3.2.1
MCLK (Main Clock) Tree
2.3.2.2
CPUCLK (Processor Clock)
2.3.2.3
ULPCLK (Low-Power Clock)
2.3.2.4
MFCLK (Middle Frequency Clock)
2.3.2.5
LFCLK (Low-Frequency Clock)
2.3.2.6
ADCCLK (ADC Sample Period Clock)
2.3.2.7
External Clock Output (CLK_OUT)
2.3.2.8
Direct Clock Connections for Infrastructure
2.3.3
Clock Tree
2.3.3.1
Peripheral Clock Source Selection
2.3.4
Clock Monitors
2.3.4.1
MCLK Monitor
2.3.4.2
Startup Monitors
2.3.4.2.1
LFOSC Startup Monitor
2.3.5
Frequency Clock Counter (FCC)
2.3.5.1
Using the FCC
2.3.5.2
FCC Frequency Computation and Accuracy
2.4
System Controller (SYSCTL)
2.4.1
Resets and Device Initialization
2.4.1.1
Reset Levels
2.4.1.1.1
Power-on Reset (POR) Reset Level
2.4.1.1.2
Brownout Reset (BOR) Reset Level
2.4.1.1.3
Boot Reset (BOOTRST) Reset Level
2.4.1.1.4
System Reset (SYSRST) Reset Level
2.4.1.1.5
CPU-only Reset (CPURST) Reset Level
2.4.1.2
Initial Conditions After POR
2.4.1.3
NRST Pin
2.4.1.4
SWD Pins
2.4.1.5
Generating Resets in Software
2.4.1.6
Reset Cause
2.4.1.7
Peripheral Reset Control
2.4.1.8
Boot Fail Handling
2.4.2
Operating Mode Selection
2.4.3
Asynchronous Fast Clock Requests
2.4.4
SRAM Write Protection
2.4.5
Flash Wait States
2.4.6
Shutdown Mode Handling
2.4.7
Configuration Lockout
2.4.8
System Status
2.4.9
Error Handling
2.4.10
SYSCTL Events
2.4.10.1
CPU Interrupt Event (CPU_INT)
2.5
Quick Start Reference
2.5.1
Default Device Configuration
2.5.2
Leveraging MFCLK
2.5.3
Optimizing Power Consumption in STOP Mode
2.5.4
Optimizing Power Consumption in STANDBY Mode
2.5.5
Optimizing for Lowest Wakeup Latency
2.5.6
Optimizing for Lowest Peak Current in RUN/SLEEP Mode
2.6
SYSCTL_C1103_C1104 Registers
3
CPU
3.1
Overview
3.2
Arm Cortex-M0+ CPU
3.2.1
CPU Register File
3.2.2
Stack Behavior
3.2.3
Execution Modes and Privilege Levels
3.2.4
Address Space and Supported Data Sizes
3.3
Interrupts and Exceptions
3.3.1
Peripheral Interrupts (IRQs)
3.3.1.1
Nested Vectored Interrupt Controller (NVIC)
3.3.1.2
Interrupt Groups
3.3.1.3
Wake Up Controller (WUC)
3.3.2
Interrupt and Exception Table
3.3.3
Processor Lockup Scenario
3.4
CPU Peripherals
3.4.1
System Control Block (SCB)
3.5
Read-Only Memory (ROM)
3.6
CPUSS Registers
3.7
WUC Registers
4
DMA
4.1
DMA Overview
4.2
DMA Operation
4.2.1
Addressing Modes
4.2.2
Channel Types
4.2.3
Transfer Modes
4.2.3.1
Single Transfer
4.2.3.2
Block Transfer
4.2.3.3
Repeated Single Transfer
4.2.3.4
Repeated Block Transfer
4.2.3.5
Stride Mode
4.2.4
Extended Modes
4.2.4.1
Fill Mode
4.2.4.2
Table Mode
4.2.5
Initiating DMA Transfers
4.2.6
Stopping DMA Transfers
4.2.7
Channel Priorities
4.2.8
Burst Block Mode
4.2.9
Using DMA with System Interrupts
4.2.10
DMA Controller Interrupts
4.2.11
DMA Trigger Event Status
4.2.12
DMA Operating Mode Support
4.2.12.1
Transfer in RUN Mode
4.2.12.2
Transfer in SLEEP Mode
4.2.12.3
Transfer in STOP Mode
4.2.12.4
Transfers in STANDBY Mode
4.2.13
DMA Address and Data Errors
4.2.14
Interrupt and Event Support
4.3
DMA Registers
5
NVM (Flash)
5.1
NVM Overview
5.1.1
Key Features
5.1.2
System Components
5.1.3
Terminology
5.2
Flash Memory Bank Organization
5.2.1
Banks
5.2.2
Flash Memory Regions
5.2.3
Addressing
5.2.3.1
Flash Memory Map
5.2.4
Memory Organization Examples
5.3
Flash Controller
5.3.1
Overview of Flash Controller Commands
5.3.2
NOOP Command
5.3.3
PROGRAM Command
5.3.3.1
Program Bit Masking Behavior
5.3.3.2
Programming Less Than One Flash Word
5.3.3.3
Target Data Alignment (Devices with Single Flash Word Programming Only)
5.3.3.4
Target Data Alignment (Devices With Multiword Programming)
5.3.3.5
Executing a PROGRAM Operation
5.3.4
ERASE Command
5.3.4.1
Erase Sector Masking Behavior
5.3.4.2
Executing an ERASE Operation
5.3.5
READVERIFY Command
5.3.5.1
Executing a READVERIFY Operation
5.3.6
BLANKVERIFY Command
5.3.6.1
Executing a BLANKVERIFY Operation
5.3.7
Command Diagnostics
5.3.7.1
Command Status
5.3.7.2
Address Translation
5.3.7.3
Pulse Counts
5.3.8
Overriding the System Address With a Bank ID, Region ID, and Bank Address
5.3.9
FLASHCTL Events
5.3.9.1
CPU Interrupt Event Publisher
5.4
Write Protection
5.4.1
Write Protection Resolution
5.4.2
Static Write Protection
5.4.3
Dynamic Write Protection
5.4.3.1
Configuring Protection for the MAIN Region
5.4.3.2
Configuring Protection for the NONMAIN Region
5.5
Read Interface
5.5.1
Bank Address Swapping
5.6
FLASHCTL Registers
6
Events
6.1
Events Overview
6.1.1
Event Publisher
6.1.2
Event Subscriber
6.1.3
Event Fabric Routing
6.1.3.1
CPU Interrupt Event Route (CPU_INT)
6.1.3.2
DMA Trigger Event Route (DMA_TRIGx)
6.1.3.3
Generic Event Route (GEN_EVENTx)
6.1.4
Event Routing Map
6.1.5
Event Propagation Latency
6.2
Events Operation
6.2.1
CPU Interrupt
6.2.2
DMA Trigger
6.2.3
Peripheral to Peripheral Event
6.2.4
Extended Module Description Register
6.2.5
Using Event Registers
6.2.5.1
Event Registers
6.2.5.2
Configuring Events
6.2.5.3
Responding to CPU Interrupts in Application Software
6.2.5.4
Hardware Event Handling
7
IOMUX
7.1
IOMUX Overview
7.1.1
IO Types and Analog Sharing
7.2
IOMUX Operation
7.2.1
Peripheral Function (PF) Assignment
7.2.2
Logic High to Hi-Z Conversion
7.2.3
Logic Inversion
7.2.4
SHUTDOWN Mode Wakeup Logic
7.2.5
Pullup/Pulldown Resistors
7.2.6
Drive Strength Control
7.2.7
Hysteresis and Logic Level Control
7.3
IOMUX (PINCMx) Register Format
7.4
IOMUX Registers
8
GPIO
8.1
GPIO Overview
8.2
GPIO Operation
8.2.1
GPIO Ports
8.2.2
GPIO Read/Write Interface
8.2.3
GPIO Input Glitch Filtering and Synchronization
8.2.4
GPIO Fast Wake
8.2.5
GPIO DMA Interface
8.2.6
Event Publishers and Subscribers
8.3
GPIO Registers
9
ADC
9.1
ADC Overview
9.2
ADC Operation
9.2.1
ADC Core
9.2.2
Voltage Reference Options
9.2.3
Generic Resolution Modes
9.2.4
Hardware Averaging
9.2.5
ADC Clocking
9.2.6
Common ADC Use Cases
9.2.7
Power Down Behavior
9.2.8
Sampling Trigger Sources and Sampling Modes
9.2.8.1
AUTO Sampling Mode
9.2.8.2
MANUAL Sampling Mode
9.2.9
Sampling Period
9.2.10
Conversion Modes
9.2.11
Data Format
9.2.12
Advanced Features
9.2.12.1
Window Comparator
9.2.12.2
DMA and FIFO Operation
9.2.12.3
Analog Peripheral Interconnection
9.2.13
Status Register
9.2.14
ADC Events
9.2.14.1
CPU Interrupt Event Publisher (CPU_INT)
9.2.14.2
Generic Event Publisher (GEN_EVENT)
9.2.14.3
DMA Trigger Event Publisher (DMA_TRIG)
9.2.14.4
Generic Event Subscriber (FSUB_0)
9.3
ADC0 Registers
10
VREF
10.1
VREF Overview
10.2
VREF Operation
10.2.1
Internal Reference Generation
10.3
VREF Registers
11
UART
11.1
UART Overview
11.1.1
Purpose of the Peripheral
11.1.2
Features
11.1.3
Functional Block Diagram
11.2
UART Operation
11.2.1
Clock Control
11.2.2
Signal Descriptions
11.2.3
General Architecture and Protocol
11.2.3.1
Transmit Receive Logic
11.2.3.2
Bit Sampling
11.2.3.3
Majority Voting Feature
11.2.3.4
Baud Rate Generation
11.2.3.5
Data Transmission
11.2.3.6
Error and Status
11.2.3.7
Local Interconnect Network (LIN) Support
11.2.3.7.1
LIN Responder Transmission Delay
11.2.3.8
Flow Control
11.2.3.9
Idle-Line Multiprocessor
11.2.3.10
9-Bit UART Mode
11.2.3.11
RS485 Support
11.2.3.12
DALI Protocol
11.2.3.13
Manchester Encoding and Decoding
11.2.3.14
IrDA Encoding and Decoding
11.2.3.15
ISO7816 Smart Card Support
11.2.3.16
Address Detection
11.2.3.17
FIFO Operation
11.2.3.18
Loopback Operation
11.2.3.19
Glitch Suppression
11.2.4
Low Power Operation
11.2.5
Reset Considerations
11.2.6
Initialization
11.2.7
Interrupt and Events Support
11.2.7.1
CPU Interrupt Event Publisher (CPU_INT)
11.2.7.2
DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
11.2.8
Emulation Modes
11.3
UART0 Registers
12
SPI
12.1
SPI Overview
12.1.1
Purpose of the Peripheral
12.1.2
Features
12.1.3
Functional Block Diagram
12.1.4
External Connections and Signal Descriptions
12.2
SPI Operation
12.2.1
Clock Control
12.2.2
General Architecture
12.2.2.1
Chip Select and Command Handling
12.2.2.1.1
Chip Select Control
12.2.2.1.2
Command Data Control
12.2.2.2
Data Format
12.2.2.3
Delayed data sampling
12.2.2.4
Clock Generation
12.2.2.5
FIFO Operation
12.2.2.6
Loopback mode
12.2.2.7
DMA Operation
12.2.2.8
Repeat Transfer mode
12.2.2.9
Low Power Mode
12.2.3
Protocol Descriptions
12.2.3.1
Motorola SPI Frame Format
12.2.3.2
Texas Instruments Synchronous Serial Frame Format
12.2.4
Reset Considerations
12.2.5
Initialization
12.2.6
Interrupt and Events Support
12.2.6.1
CPU Interrupt Event Publisher (CPU_INT)
12.2.6.2
DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
12.2.7
Emulation Modes
12.3
SPI Registers
13
I2C
13.1
I2C Overview
13.1.1
Purpose of the Peripheral
13.1.2
Features
13.1.3
Functional Block Diagram
13.1.4
Environment and External Connections
13.2
I2C Operation
13.2.1
Clock Control
13.2.1.1
Clock Select and I2C Speed
13.2.1.2
Clock Startup
13.2.2
Signal Descriptions
13.2.3
General Architecture
13.2.3.1
I2C Bus Functional Overview
13.2.3.2
START and STOP Conditions
13.2.3.3
Data Format with 7-Bit Address
13.2.3.4
Acknowledge
13.2.3.5
Repeated Start
13.2.3.6
SCL Clock Low Timeout
13.2.3.7
Clock Stretching
13.2.3.8
Dual Address
13.2.3.9
Arbitration
13.2.3.10
Multiple Controller Mode
13.2.3.11
Glitch Suppression
13.2.3.12
FIFO operation
13.2.3.12.1
Flushing Stale Tx Data in Target Mode
13.2.3.13
Loopback mode
13.2.3.14
Burst Mode
13.2.3.15
DMA Operation
13.2.3.16
Low-Power Operation
13.2.4
Protocol Descriptions
13.2.4.1
I2C Controller Mode
13.2.4.1.1
Controller Configuration
13.2.4.1.2
Controller Mode Operation
13.2.4.1.3
Read On TX Empty
13.2.4.2
I2C Target Mode
13.2.4.2.1
Target Mode Operation
13.2.5
Reset Considerations
13.2.6
Initialization
13.2.7
Interrupt and Events Support
13.2.7.1
CPU Interrupt Event Publisher (CPU_INT)
13.2.7.2
DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
13.2.8
Emulation Modes
13.3
I2C Registers
14
CRC
14.1
CRC Overview
14.1.1
CRC16-CCITT
14.2
CRC Operation
14.2.1
CRC Generator Implementation
14.2.2
Configuration
14.2.2.1
Bit Order
14.2.2.2
Byte Swap
14.2.2.3
Byte Order
14.2.2.4
CRC C Library Compatibility
14.3
CRC Registers
15
Timers (TIMx)
15.1
TIMx Overview
15.1.1
TIMG Overview
15.1.1.1
TIMG Features
15.1.1.2
Functional Block Diagram
15.1.2
TIMA Overview
15.1.2.1
TIMA Features
15.1.2.2
Functional Block Diagram
15.1.3
TIMx Instance Configuration
15.2
TIMx Operation
15.2.1
Timer Counter
15.2.1.1
Clock Source Select and Prescaler
15.2.1.1.1
Internal Clock and Prescaler
15.2.1.1.2
External Signal Trigger
15.2.1.2
Repeat Counter (TIMA only)
15.2.2
Counting Mode Control
15.2.2.1
One-shot and Periodic Modes
15.2.2.2
Down Counting Mode
15.2.2.3
Up/Down Counting Mode
15.2.2.4
Up Counting Mode
15.2.2.5
Phase Load (TIMA only)
15.2.3
Capture/Compare Module
15.2.3.1
Capture Mode
15.2.3.1.1
Input Selection, Counter Conditions, and Inversion
15.2.3.1.1.1
CCP Input Edge Synchronization
15.2.3.1.1.2
CCP Input Pulse Conditions
15.2.3.1.1.3
Counter Control Operation
15.2.3.1.1.4
CCP Input Filtering
15.2.3.1.1.5
Input Selection
15.2.3.1.2
Use Cases
15.2.3.1.2.1
Edge Time Capture
15.2.3.1.2.2
Period Capture
15.2.3.1.2.3
Pulse Width Capture
15.2.3.1.2.4
Combined Pulse Width and Period Time
15.2.3.1.3
QEI Mode (TIMG with QEI support only)
15.2.3.1.3.1
QEI With 2-Signal
15.2.3.1.3.2
QEI With Index Input
15.2.3.1.3.3
QEI Error Detection
15.2.3.1.4
Hall Input Mode (TIMG with QEI support only)
15.2.3.2
Compare Mode
15.2.3.2.1
Edge Count
15.2.4
Shadow Load and Shadow Compare
15.2.4.1
Shadow Load (TIMG4-7, TIMA only)
15.2.4.2
Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
15.2.5
Output Generator
15.2.5.1
Configuration
15.2.5.2
Use Cases
15.2.5.2.1
Edge-Aligned PWM
15.2.5.2.2
Center-Aligned PWM
15.2.5.2.3
Asymmetric PWM (TIMA only)
15.2.5.2.4
Complementary PWM With Deadband Insertion (TIMA only)
15.2.5.3
Forced Output
15.2.6
Fault Handler (TIMA only)
15.2.6.1
Fault Input Conditioning
15.2.6.2
Fault Input Sources
15.2.6.3
Counter Behavior With Fault Conditions
15.2.6.4
Output Behavior With Fault Conditions
15.2.7
Synchronization With Cross Trigger
15.2.7.1
Main Timer Cross Trigger Configuration
15.2.7.2
Secondary Timer Cross Trigger Configuration
15.2.8
Low Power Operation
15.2.9
Interrupt and Event Support
15.2.9.1
CPU Interrupt Event Publisher (CPU_INT)
15.2.9.2
Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
15.2.9.3
Generic Subscriber Event Example (COMP to TIMx)
15.2.10
Debug Handler (TIMA Only)
15.3
TIMx Registers
16
WWDT
16.1
WWDT Overview
16.1.1
Watchdog Mode
16.1.2
Interval Timer Mode
16.2
WWDT Operation
16.2.1
Mode Selection
16.2.2
Clock Configuration
16.2.3
Low-Power Mode Behavior
16.2.4
Debug Behavior
16.2.5
WWDT Events
16.2.5.1
CPU Interrupt Event Publisher (CPU_INT)
16.3
WWDT Registers
17
Debug
17.1
Overview
17.1.1
Debug Interconnect
17.1.2
Physical Interface
17.1.3
Debug Access Ports
17.2
Debug Features
17.2.1
Processor Debug
17.2.1.1
Breakpoint Unit (BPU)
17.2.1.2
Data Watchpoint and Trace Unit (DWT)
17.2.2
Peripheral Debug
17.2.3
EnergyTrace Technology
17.3
Behavior in Low Power Modes
17.4
Restricting Debug Access
17.5
Mailbox (DSSM)
17.5.1
DSSM Events
17.5.1.1
CPU Interrupt Event (CPU_INT)
17.5.2
DEBUGSS Registers
18
Revision History
12.2.2
General Architecture