SLAU917B October   2023  – February 2024 AFE20408

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Hardware Setup
      1. 2.1.1 Hardware Theory of Operation
      2. 2.1.2 Jumper Definitions
      3. 2.1.3 Connector Definitions
      4. 2.1.4 Test Points
    2. 2.2 Hardware Overview
      1. 2.2.1 Electrostatic Discharge Caution
      2. 2.2.2 Connecting the FTDI Digital Controller
      3. 2.2.3 SPI Configuration
      4. 2.2.4 I2C Configuration
      5. 2.2.5 PAON Open Drain Circuit
  9. 3Software
    1. 3.1 Software Setup
      1. 3.1.1 Software Installation
    2. 3.2 Software Overview
      1. 3.2.1 Launching the Software
      2. 3.2.2 Software Features
        1. 3.2.2.1 Low Level Configuration Page
        2. 3.2.2.2 High Level Configuration Page
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1.     Trademarks
  12. 6Revision History

3.2.2.2 High Level Configuration Page

The High Level Configuration page is used to set the configuration of the AFE20408EVM GUI. The page is comprised of two tabs: DAC Control and ADC Control. These two tabs act as shortcuts to configure the AFE20408 for basic functionality and testing.

Figure 4-7 shows the DAC Control tab of the High Level Configuration page. This tab is used to set the range and outputs for the DACs. Alarms and status information is also displayed on this tab.

GUID-20231109-SS0I-K9DT-QJH4-SRC8HK57FMPK-low.pngFigure 3-7 DAC Control Tab of the High Level Configuration Page

DACs

DACs DACA0, DACA2, DACB0, and DACB2 are powered on by checking the respective PDACxx box. DACs DACA1, DACA3, DACB1, and DACB3 are powered on by checking the respective PDACxx box and by clicking the DRVEN_DACxx box. Write to the DAC buffers by entering hex values into the DACxx_BUFFER boxes.

DRIVE ENABLE

By default, all of the DACs are connected to the software drive enable. To enable the DRVEN hardware pins, de-select the software DRVEN and select one of the hardware DRVEN options (DRVEN0, DRVEN1, or FLEXIO). The DRVEN0 and DRVEN1 hardware pins be controlled by the GUI if jumper J23 1-2 and 3-4 are shorted.

OUT PINS

By default, OUTA0, OUTA2, OUTB0, and OUTB2 are connected to the VSSA/VSSB power supply. The CLAMP_SEL_OUTxx box sets the OUTxx pins to the respective DACxx pin. Table 4-1 shows the Output pin configurations.

Table 3-1 Output Pin CLAMP Configuration
Output PinCLAMP BitCLAMP_SEL = 0CLAMP_SEL = 1
OUTA0CLAMP_SEL_OUTA0VSSADACA1
OUTA2CLAMP_SEL_OUTA2VSSADACA3
OUTB0CLAMP_SEL_OUTB0VSSBDACB1
OUTB2CLAMP_SEL_OUTB2VSSBDACB3

Furthermore, the output pins can switch between the respective CLAMP and even DACs using the even DAC's DRVEN bit. Table 4-2 shows the DRVEN configurations.

Table 3-2 Output Pin DRVEN Configuration
Output PinDRVEN BitDRVEN = 0DRVEN = 1
OUTA0DRVEN_DACA0DACA1/VSSADACA0
OUTA2DRVEN_DACA2DACA3/VSSADACA2
OUTB0DRVEN_DACB0DACB1/VSSBDACB0
OUTB2DRVEN_DACB2DACB3/VSSBDACB2

Figure 4-8 shows the ADC Control tab from the High Level Configuration page. This tab configures and reads data from the ADC in the AFE20408.

GUID-20231109-SS0I-DMH0-RWJ9-NGQ5SL8K4KMZ-low.pngFigure 3-8 ADC Control Tab of the High Level Configuration Page