SLAZ091Z October   2012  – May 2021 CC430F5125

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RGZ48
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC39
    2. 6.2  ADC42
    3. 6.3  ADC69
    4. 6.4  AES1
    5. 6.5  BSL7
    6. 6.6  BSL14
    7. 6.7  COMP10
    8. 6.8  CPU21
    9. 6.9  CPU22
    10. 6.10 CPU36
    11. 6.11 CPU40
    12. 6.12 CPU46
    13. 6.13 CPU47
    14. 6.14 DMA4
    15. 6.15 DMA7
    16. 6.16 DMA10
    17. 6.17 EEM17
    18. 6.18 EEM19
    19. 6.19 EEM23
    20. 6.20 JTAG26
    21. 6.21 JTAG27
    22. 6.22 PMM11
    23. 6.23 PMM12
    24. 6.24 PMM14
    25. 6.25 PMM15
    26. 6.26 PMM18
    27. 6.27 PMM20
    28. 6.28 PMM26
    29. 6.29 PORT15
    30. 6.30 PORT19
    31. 6.31 PORT29
    32. 6.32 RF1A1
    33. 6.33 RF1A2
    34. 6.34 RF1A3
    35. 6.35 RF1A5
    36. 6.36 RF1A6
    37. 6.37 RF1A8
    38. 6.38 SYS12
    39. 6.39 SYS16
    40. 6.40 UCS11
    41. 6.41 USCI26
    42. 6.42 USCI30
    43. 6.43 USCI34
    44. 6.44 USCI35
    45. 6.45 USCI39
    46. 6.46 USCI40
  7. 7Revision History

6.44 USCI35

USCI Module

Category

Functional

Function

Violation of setup and hold times for (repeated) start in I2C master mode

Description

In I2C master mode, the setup and hold times for a (repeated) START, tSU,STA and tHD,STA respectively, can be violated if SCL clock frequency is greater than 50kHz in standard mode (100kbps). As a result, a slave can receive incorrect data or the I2C bus can be stalled due to clock stretching by the slave.

Workaround

If using repeated start, ensure SCL clock frequencies is < 50kHz in I2C standard mode (100 kbps).