SLAZ143I October 2012 – May 2021 MSP430F156
I2C Module
Functional
Master/Slave looses data on reception (lost RXRDYIFG).
If the I2C data register I2CDRB (I2CDRW) is read at the same time that data is loaded from the internal I2C shift register into I2CDRB (I2CDRW), then the received data is lost and no corresponding receive ready interrupt (RXRDYIFG) is generated. Following RXRDYIFG interrupts are processed but the missing byte cannot be recovered.
Do not read the I2CDRB(I2CDRW) register while data is being loaded into it. This can be ensured by reading this register in a timely manner using any one of the following methods:
1) Handle RXRDYIFG events with all other interrupt sources disabled.
2) Use the DMA for receiving incoming I2C data. The DMA interrupt or ARDYIFG interrupt can be used to initiate further processing of received data.
3) Enable nested interrupts to allow immediate processing of RXRDYIFG interrupts. (Care must be taken to avoid stack overflows).